Hello,
I want to activate the ECC on caches on TMS570LC457 and for safety reasons I need to have fine control of the sanctions applied in case of uncorrectable errors so that to reach a safe state.
While reading the cortex-R5 TRM (ARM DDI 0460D) the last paragraph of section 3.8.4 about Abort handler indicates that in case a synchronous error occurs while in the abort handler then "the processor loops until the next interrupt" and "LR and SPSR values for the original abort are lost".
The first part of this sentence is not so clear in my mind and I'd like to confirm what the behavior of the TMS570LC4357 would be in the following case:
1. An abort exception is taken for any reason (synchronous or asynchronous abort)
2. Abort handler is entered and asynchronous aborts are automatically masked (CPSR.A set when entering IRQ/FIQ or Abort)
3. A synchronous abort occurs due to an ECC error when accessing cache
4. ?? What is the actual state of the processor and what will it perform, will it loop doing nothing waiting for a new interrupt and treat this interrupt as if not abort occurred at all ??
I am already aware that avoiding step 2. by ensuring that non synchronous abort could occur (by setting the memory space used by the handler as non cacheable as an example) would solve my issue and the point of this question is really to help me understand what would happen in step 4.
Thanks,