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TMS570LS1224: Sram self test for SRAM_ECC_ERROR_FORCING_2BIT is failing.

Bharat@Honeywell
Prodigy 180 points
Part Number: TMS570LS1224
Other Parts Discussed in Thread: HALCOGEN

Hello Team,

I am using Safe ti Diagnostic library 2.3.1.  I am testing the SRAM with Safe ti Diagnostic library API's SL_SelfTest_SRAM.

the following test case is failing 

retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM);

when i debugged i found that sl_esmREG->SR1[2] is always zero. so the below condition is always failing.

if ((((uint32)&sramEccTestBuff[2] & TCRAM_RAMUERRADDR_UNC_ERRADD) == ram1uerraddr)
&& (((uint32)&sramEccTestBuff[3] & TCRAM_RAMUERRADDR_UNC_ERRADD) == (ram2uerraddr)) &&
((uint32)(1u << ESM_G3ERR_B1TCM_ECC_UNCORR) == (sl_esmREG->SR1[2] & (uint32)(1u << ESM_G3ERR_B1TCM_ECC_UNCORR)))&&
((uint32)(1u << ESM_G3ERR_B0TCM_ECC_UNCORR) == (sl_esmREG->SR1[2] & (uint32)(1u << ESM_G3ERR_B0TCM_ECC_UNCORR)))) {

As per my understanding SRAM_ECC_ERROR_FORCING_2BIT cause ESM group3  errors.

Please let me why sl_esmREG->SR1[2] is alwyas zero in my case? where am i doing wrong?

Regards,

Bharat

  • 0
    TI__Guru 59540 points
    Hello Bharat,

    First, so you are aware there is a new release of the SafeTI Diagnostic Library (SDL). The latest is version 2.4.0. I am not aware if there were any reported issues with this test in the past, but it might be worth having a look at the release notes.

    This sl_esmSR1[2] is actually the ESM Status Register 3 (ESMSR3) register so the fact that it is showing as 0 indicates that the error was not flagged. This may be possible if the write to the ECC data did not happen to corrupt the ECC or if ECC is not enabled for export during startup. Are you using the Halcogen based startup code for boot? Can you check to insure ECC is enabled as part of your boot configuration in Halcogen?