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TMS570LS1224: How to test the safety feature PCR Access Management

Bharat@Honeywell
Prodigy 180 points
Part Number: TMS570LS1224

Hello Team,

How to test the safety feature PCR Access Management. I didn't see any API in the Safe TI diagnostic library.

The Safety manual says that 

'' A software test can be utilized to test basic functionality as well as to inject diagnostic errors and check for proper error response. Such a test can be executed at boot or periodically. Software requirements necessary are defined by the software implemented by the system integrator. "

Can someone elaborate what kind of errors/faults which we should inject to verify this functionality. 

Regards,

Bharat

 

  • 0
    TI__Guru**** 190446 points
    Hello Bharat,

    The PCR manages the accesses to the peripheral registers and peripheral controller memories. The PCR also manages the accesses to the system module registers required to configure the device’s clocks, interrupts, etc.

    The PCR module PPROTSETx registers contain one bit per peripheral select quadrant. These bits define the access permissions to the peripheral register frames. If the CPU attempts to write to a peripheral register for which it does not have the correct permissions, a protection violation is detected and an Abort occurs.

    The PCR module PMPROTSETx registers contain one bit per peripheral memory frame. These bits define the access permissions to the peripheral memory frames. If the CPU attempts to write to a peripheral memory for which it does not have the correct permissions, a protection violation is detected and an Abort occurs.
  • 0 in reply to QJ Wang
    Prodigy 180 points
    Hello Wang,

    Thanks for your Reply.

    The PCR module registers contain one bit per peripheral select quadrant. But it is not giving enough information like which bit corresponding to which peripheral (like mibADC,Mibspi,i2c .....)

    The documentation of PCR doesn't tell how configure/enable/disable/test the peripherals. The mapping of Peripherals and its corresponding bit in the PCR register is missing.

    Can you please elobrate how can i selectivey enable/disable/memory protect a Peripheral by using the PCR registers??

    Any help on this is appreciated.

    Regards,
    Bharat
  • 0 in reply to Bharat@Honeywell
    TI__Guru**** 190446 points

    Hello Bharat,

    The peripheral selects (PS) are fractionated into 4 quadrants of 256 bytes each. A peripheral can be mapped to each quadrant as long as the register mapping does't not exceed 256 bytes.

    If a peripheral exceeds 256 bytes for register mapping, it can be mapped into 2 or more consecutive quadrants using the following rules.

    < 256 bytes: 1 quadrant required                                                      for example: PS[16] for GIO

    >256bytes and <512 bytes: 2 quadrants required                             for example: PS[23] for FTU, or PS[22] for HTU1 and HTU2

    >512 bytes and < 1kB: 4 quadrants required                                    for example: PS[12] or PS[13] for flexray, PS[6] for LIN and SCI

    This is Table 6-21 in Datasheet

  • 0 in reply to QJ Wang
    TI__Guru**** 190446 points
    PPROTSET0 is one of the peripheral protection set register:

    Bit 0 is for PS0 Quadrant 0 protection set

    Bit 1 is for PS0 Quadrant 1 protection set

    Bit 2 is for PS0 Quadrant 2 protection set

    Bit 3 is for PS0 Quadrant 3 protection set

    Bit 4 is for PS1 Quadrant 0 protection set

    Bit 5 is for PS1 Quadrant 1 protection set

    Bit 6 is for PS1 Quadrant 2 protection set

    Bit 7 is for PS1 Quadrant 3 protection set

    Bit 8 is for PS2 Quadrant 0 protection set --> MibSPI1

    Bit 9 is for PS2 Quadrant 1 protection set --> MibSPI1

    Bit 10 is for PS2 Quadrant 2 protection set -->SPI2

    Bit 11 is for PS2 Quadrant 3 protection set --> SPI2

    ....
  • 0 in reply to QJ Wang
    TI__Guru**** 190446 points

    The slave uses 2 quadrants:

    Let us consider PS[2] for example.

    MibSPI1 uses Quad0 and Quad1, and SPI2 uses Quad2 and Quad3.

    The bit corresponding to quadrant 0, protects both quadrants 0 and 1. The bit corresponding to quadrant 1 is not implemented.

    The bit corresponding to quadrant 2, protects both quadrants 2 and 3. The bit corresponding to quadrant 3 is not implemented.

    For PS2, bit 8 protects the first 512 bytes, i.e. the quadrants 0 and 1. Bit 9 is not implemented.

    Bit 10 protects the second 512 bytes, i.e. the quadrants 2 and 3. Bit 11 is not implemented.

    The slave uses all the four quadrants

    Only the bit corresponding to quadrant 0 of PSn is implemented. It protects the whole 1Kbyte frame. The remaining three bits are not implemented.

    Let us consider PS[12] for flexray

    Bit 16 protects the whole address range of the 1Kbyte PS[12] frame. Bits 9, 10 and 11 are not implemented.