Current FRAM has ~10**14 “write cycle endurance”. Is that “virtually unlimited”?
My understanding is that reading FRAM is destructive and the controller automatically generates a write cycle after each read cycle to restore contends. Thus if the FRAM is used to store code and the MCLK is at 16MHz, there may be up to 1.6*10**6 “write cycles” per second. The worst case is when there are many jumps in the code.
There are 3.2*10**6 seconds per year. This translate to 10**14 “write cycles” in two years. Depends on where the jumps are placed, those write cycle may hit some of the bit cells very often. I think those bit cells will not endure for too many years.
Is the above concern justified?