MSP430F5419A : USCI interrupt rx problem with SMCLK and LPM3 mode

Hi,

I'm working on a MSP430F5419A trying to use the USCI modules in uart mode. Here is my config :

- Operating mode : LPM3

- USCI_A0 : 115200 bauds, SMCLK(4MHz), no parity, 8 bits, 1 stop bit, interrupt on reception allowed

- USC :

32kHz -> XT1 -> FLL -> DCO 4Mhz -> SMCLK 4Mhz & MCLK 4MHz

32kHz -> XT1 -> ACLK

I succeed in sending characters to an hyperterminal, but the problem comes from the rx interrupt. I well enter in the interrupt, first characters are correct but then what it is stored in UCA0RXBUF is completely wrong.

I tested many configuration, changing the baud rate for example (no influence) and other operating mode + clock config :

- LPM0 (or active mode) + USCI with SMCLK = no problem (but consumption is not acceptable for us)

- LPM3 + USCI with ACLK = no problem (but maximum baud rate is too low for us)

I know that SMCLK is not active during LPM3, but I see on a scope that SMCLK become active during character reception (SMCLK become active 1.5µs after first falling edge on USCI_A0_RX). I usually work on the MSP430F247, using uart module @19200 bauds with SMCLK@1MHz and LPM3 mode and I never observed this problem.

Maybe this problem is known in MSP430F5x ?

See my test code below :

void main(void)
{
  // clocks configuration : ACLK = XT1 = 32.768kHz, MCLK = SMCLK = DC0/2 = 32768*(1+121)/2 = 4MHz
  WDTCTL = ( WDTPW | WDTHOLD );   // stop watchdog timer
 
  P7SEL |= 0x03;                            // Select XT1
 
  UCSCTL6 &= ~(XT1OFF);                     // XT1 On
  UCSCTL6 = 0xC1CC;                         // Internal load cap
 
  UCSCTL3 = 0;                              // Set DCO FLL reference = XT1
  UCSCTL4 = SELS_4 + SELM_4;                // Set ACLK = XT1
 
  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
  UCSCTL1 = DCORSEL_4;                      // Select DCO range 8MHz operation
  UCSCTL2 = FLLD_1 + 121;                   
  __bic_SR_register(SCG0);                  // Enable the FLL control loop
 
  __delay_cycles(125000);
 
  // Loop until XT1,XT2 & DCO fault flag is cleared
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
 
  // Init uartA0
  UCA0CTL1 = (UCSSEL_2 | UCSWRST);              // set UCSWRST, SMCLK
  UCA0CTL0 = 0;                                 // no parity, 8 bits, LSB first, 1 stop bit, async mode
  UCA0BR0 = 34;                                 // to get 115200 bauds if SMCLK = 4MHz
  UCA0BR1 = 0;
  // I/Os config
  P3DIR |= BIT4;
  P3DIR &= ~BIT5;
  P3SEL |= 0x30;
  UCA0CTL1 = UCSSEL_2;                          // clear UCSWRST --> uart OK
 
  // Handle interrupt
  UCA0IFG &= ~UCRXIFG;
  UCA0IE |= UCRXIE;

  Timers_Configure();
  Timers_Start_Periodical_Event();  
  Start_Watchdog_Timer();
 
  _EINT();
 
  while(1)
  {    

    LPM3;  
    _NOP();   
    Start_Watchdog_Timer();
  }
}

u8 buffer_temp[256];
u16 index=0;

#pragma vector = USCI_A0_VECTOR
__interrupt void uartA0_irq(void)
{
  u16 temp = UCA0IV;
 
  if(temp==0x02)
  {
    buffer_temp[index++] = UCA0RXBUF;
    index %= 256;
  }
  else if(temp==0x04)
  {
    UCA0IFG &= ~UCTXIFG;
  }
 
  LPM3_EXIT;
}

Thanks in advance for your support