MSP4305324 configure UCS: XT2 is 4Mhz MCLK is 8M

Don't see any reason for running DCO when there is XT2 already present on board. Use 8 MHz XT2 or 24 MHz XT2 and scale it down (divide by 2, 4, 8...) to requested MCLK.

There are several differences between this code and the equivalent driverlib functions (UCS_XT2Start(), UCS_clockSignalInit(), UCS_initFLLSettle()). I'm too lazy to list them here; why don't you just use driverlib, or copy the code from there?

I used MSP430F55xx_UCS_02.c as a basis for the following. Measured MCLK output, which was roughly 2x the input clock on X2.

#include <msp430.h>

int main(void)
{
  volatile unsigned int i;

  WDTCTL = WDTPW+WDTHOLD;                   // Stop WDT
  P1DIR |= BIT1;                            // P1.1 output

  P1DIR |= BIT0;                            // ACLK set out to pins
  P1SEL |= BIT0;                           
  P2DIR |= BIT2;                            // SMCLK set out to pins
  P2SEL |= BIT2;                           
  P7DIR |= BIT7;                            // MCLK set out to pins
  P7SEL |= BIT7;          

  P5SEL |= BIT2+BIT3;                       // Port select XT2
 
  UCSCTL3 = SELREF_5;                       // Set DCO FLL reference = XT2
  UCSCTL4 |= SELA_2;                        // Set ACLK = REFO
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx

  // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
 
  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL1 = DCORSEL_4;                      // Select DCO range 16MHz operation
  UCSCTL2 |= 1;                           // Set DCO Multiplier for 8MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (249 + 1) * 32768 = 8MHz
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
  __delay_cycles(250000);
 
  while(1)
  {
    P1OUT ^= BIT0;                          // Toggle P1.0
    __delay_cycles(600000);                 // Delay
  }
}

Hopefully, this helps.

Oh, made the following changes:

1. Added the P5SEL code for XT2.

2. Changed UCSCTL3 to SELREF_5 for XT2.

3. Changed to DCORSEL_4

4. Changed multipler to 1(+1 = 2).

Probably need to set up the drive strength, capacitive loading, etc. But, I wanted to see if I could get "in the ballpark."

I would probably opt for what Zrno said, just use an 8 MHz input...