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MSP432 timers

It's mentioned the MSP432 peripherals have a 24MHz clock limit. Does this mean both TimerA and Timer32 have that limit?

Thanks,
Kirk

  • Hi Kirk,

    Timer_A definitely has this limit - it can be seen in the datasheet www.ti.com/.../msp432p401r on p. 57. I'm investigating Timer32 and will respond back when I have an answer for you.

    Regards,
    Katie
  • Hi Kirk,

    Got an update from the design guys: the Timer32 runs on MCLK and can run as fast as the processor can run at for the Vcore you are using i.e. at Vcore0 max frequency is 24MHz, and at Vcore1 max frequency is 48MHz. We'll work to make sure this gets into the next version of the datasheet too.

    Regards,
    Katie

  • But as the Timer32 can only be used to generate software IRQs, what uses does it have running at 48MHz?
    As you probably will use it as a very long sleep counter and probably will be divided by 8 etc.
    If a capture mode was implemented, then I say it would be useful to run at 48
    So are there plans for other msp432 with more advanced Timer32?

  • Long duration sleep would probably be better served by RTC- lower power consumption I would presume.
     
    What I can imagine it may be useful for is wake up by RTC, use Timer32 to trigger several potentially concurrent events with other peripherals. Seems plausible that one event from Timer32 could trigger multiple peripherals to start an action?

    Still reading and absorbing.

  • The MSP432 looks like a great chip, however, IMHO you need better timers than Timer_A. Yeah, I want buffers for the capture compare registers as in Timer_B, I want hardware events to be able to reset the counter without the need of interrupts, why can't I have them? Give me a state of the art timer that can be triggered by inputs and directly control outputs. 

  • Tony Philipsson said:
    So are there plans for other msp432 with more advanced Timer32?

     Hi Tony, I can think this can be a peripheral useful to port some TIVA code to this platform seamless so it can serve internal software timing without register scaling, is of little use on old MSP software.

     About MSP timers timer B and timerD are the better we can ask for, if an EPWM can be ported from C2000 series this can be a killer but time has to elapse and all has to be checked, about IP Property share of TI internal we are just seeing final results.

      Also porting old timer software from MSP430 to MSP432 require some care, math is different and 16 to 32 bit are to be applied to overflow and counters.

     Also on announcement MPY was mentioned but no trace is on data sheet nor on product pages.

     After this processor two missing items on MSP can have sense so why not both CAN BUS controller and ETHERNET sharing between series ?

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