MSP430F5528 I2C interface with MPU-9150

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//******************************************************************************
//  MSP430F552x Demo - USCI_B0 I2C Master TX single bytes to MSP430 Slave
//
//  Description: This demo connects two MSP430's via the I2C bus. The master
//  transmits to the slave. This is the master code. It continuously
//  transmits 00h, 01h, ..., 0ffh and demonstrates how to implement an I2C
//  master transmitter sending a single byte using the USCI_B0 TX interrupt.
//  ACLK = n/a, MCLK = SMCLK = BRCLK = default DCO = ~1.045MHz
//
// ***to be used with "MSP430F55xx_uscib0_i2c_07.c" ***
//
//                                /|\  /|\
//                MSP430F5529     10k  10k     MSP430F5529
//                   slave         |    |         master
//             -----------------   |    |   -----------------
//           -|XIN  P3.0/UCB0SDA|<-|----+->|P3.0/UCB0SDA  XIN|-
//            |                 |  |       |                 |
//           -|XOUT             |  |       |             XOUT|-
//            |     P3.1/UCB0SCL|<-+------>|P3.1/UCB0SCL     |
//            |                 |          |                 |
//
//   Bhargavi Nisarga
//   Texas Instruments Inc.
//   April 2009
//   Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************

#include <msp430.h>

unsigned char TXData,i;
unsigned char RXData;
unsigned char VALUE;
//unsigned char TXByteCtr;
int TXByteCtr;
int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P3SEL |= 0x03;                            // Assign I2C pins to USCI_B0
  UCB0CTL1 |= UCSWRST;                      // Enable SW reset
  UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC;     // I2C Master, synchronous mode
  UCB0CTL1 = UCSSEL_2 + UCSWRST;            // Use SMCLK, keep SW reset
  UCB0BR0 = 12;                             // fSCL = SMCLK/12 = ~100kHz
  UCB0BR1 = 0;
  UCB0I2CSA = 0x69;                         // Slave Address is 048h
  UCB0CTL1 &= ~UCSWRST;                     // Clear SW reset, resume operation
 //UCB0IE |= UCTXIE;                         // Enable TX interrupt
 //UCB0IE |= UCRXIE;  
//UCB0IE |= UCNACKIE;
                         // Holds TX data

  while (1)
    
  { 
    
  //for(i=0;i<10;i++);
  
    TXData = 0x75; 
     
     while (UCB0CTL1 & UCTXSTP);
    UCB0CTL1 = 0x92;// write enable
    UCB0TXBUF = TXData;
    //slave data
    
    //__delay_cycles( 1000 ); 
    UCB0CTL1 = 0x82;// read enable
    
    while((UCB0IFG ^ (UCRXIFG+UCTXIFG) ));
    //while((UCB0IFG ^ (UCRXIFG) ));
    RXData = UCB0RXBUF;
    while(UCB0CTL1 & UCTXSTT);
    RXData = UCB0RXBUF;
    UCB0CTL1 |= UCTXNACK;
    UCB0CTL1 |= UCTXSTP;
    UCB0IFG &= ~UCTXIFG;
    //UCB0IFG &= ~UCRXIFG;
    
    //
     //__no_operation();
    
    
    
    
     __no_operation();
    
  }
  
}


//------------------------------------------------------------------------------
// The USCIAB0_ISR is structured such that it can be used to transmit any
// number of bytes by pre-loading TXByteCtr with the byte count.
//------------------------------------------------------------------------------
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(UCB0IV,12))
  {
  case  0: break;                           // Vector  0: No interrupts
  case  2: break;                           // Vector  2: ALIFG
  case  4: 
   //UCB0CTL1=UCTXSTP; 
    break;                           // Vector  4: NACKIFG
  case  6: break;                           // Vector  6: STTIFG
  case  8: break;                           // Vector  8: STPIFG
  case 10:                          // Vector 10: RXIFG
  RXData = UCB0RXBUF;                     // Get RX data
    __bic_SR_register_on_exit(LPM0_bits);   // Exit active CPU
     break; 
  case 12:                                  // Vector 12: TXIFG  
    
 
    break;
  default: break;
  }
}