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Trying to set up 4 MHz external crystal osc on XT2

Dubs Mozz
Intellectual 330 points
Other Parts Discussed in Thread: MSP430F5659

Hello

Im hoping someone can help me.


I am trying to set up my MSP430F5659 with an external crystal osc on XT2 that is 4 MHz.  (note, it's a crystal, NOT an external clock - so no bypass, right?)

I'd like to setup ACLK = 4 MHZ, SMCLK = 16 MHz , MCLK = 16 MHz 

What I'm getting is a whole lot of nothing. I have a fault  OFIFG = 1 after the below routine runs.  

can anyone see my flaw? 

WDTCTL = WDTPW + WDTHOLD;

SFRIFG1 &= ~OFIFG; // clear osc flag

UCA0CTL1 = UCSWRST; // reset USCI 1

UCA0CTL0 = 0x00;

UCSCTL5 = 0x00;       // ACLK, SMCLK source divider
                                      // 0 = dont divide ACK and SMCLK

istate_t istate = __get_interrupt_state();
__disable_interrupt();                                         // Disable global interrupts

/ 

P7SEL |= 0x03;                   // Port select XT1
 
UCSCTL6 |= (XT1OFF);     // XT1 off
P7SEL |= 0x03;                    // Port select XT1

UCSCTL6 &= ~(XT2OFF);    // XT2 on

UCSCTL3 = SELREF__XT2CLK |FLLREFDIV_4 ;             // source for ffl is Xt2, div 4
                                                                                                    // output is DCO
                                                                                                     // 4 MHz div 4 = 16 MHz DCO

UCSCTL4 = SELA__XT2CLK | SELS__DCOCLK  |  SELM__DCOCLK  ;   // ack clock source is xt2 , source for mclk is DCO , source for smclk is DCO

while(BAKCTL & LOCKIO)               
BAKCTL &= ~(LOCKIO);

do                                                                 
{     // clear all osc, DCO flags
       UCSCTL7 &= ~ ( DCOFFG| XT1LFOFFG | XT1HFOFFG | XT2OFFG );
        SFRIFG1 &= ~OFIFG;
} while(SFRIFG1 & OFIFG);                             /// ***** I FAIL RIGHT HERE!!!! I ALWAYS HAVE OFIFG = 1   ******************

 
UCSCTL1 |= DCORSEL_5;                                               // MCLK = 16MHz(see data sheet  p63-- not sure I need this???)
                    

UCSCTL2 &= 0x0000;

Please - any help is much appreciated. 

thanx

Dubs

  • 0
    TI__Prodigy 335 points

    Hello Dubs,

    to enable the XT2 functionality on P7.3/P7.2 you have to set Bit2 in P7SEL (P7SEL |= BIT2;). This will activate the Xin/Xout path of the XT2-Oscillator. After the crystal is oscillating you should be able to clear the Oscillator-Fault-Flags.
    In your code you are setting P7SEL for P7.0/P7.1 which are not existing on the F5659.

    Best regards,

    Michael

  • 0 in reply to Michael Weber
    Intellectual 330 points

    Hi Michael

    Thank you for your reply. I did as you said but still have the fault.  how does the rest of it look?   


    I am supposed to 'turn on' Xt2 with  UCSCTL6 &= ~(XT2OFF);    with an external crystal osc , correct?

    please anymore help would be much appreciated. 

    Best Regards
    Dubs

  • 0 in reply to Dubs Mozz
    TI__Prodigy 335 points
    Hi Dubs,
    The XT2OFF bit if for disabling the XT2 when not used as source for any Clockpath or as reference for the FLL, but it is alright in your when you clear it. I just see that you only disable XT2OFF and keep all other bits in default state. In this case the XT2DRIVE-Setting is on the highest level and this can be to much for your XTAL.
    You should use XT2DRIVE-Level 0 (clear both XT2DRIVE-Bits) and check if it works (the XT2 Fault Flag should be stayed cleared in your do-while-loop). If you are not able to clear the fault flag try to increase the drive level step by step.
    Best regards,Michael
  • 0 in reply to Michael Weber
    Intellectual 330 points
    Hi Michael

    Thanks for your input. I've tried it. No good.
    Here's what I've got now but still same problem


    // Stop watchdog timer to prevent time out reset
    WDTCTL = WDTPW + WDTHOLD;


    //P7SEL |= BIT2;
    P7SEL |= 0x0C;

    UCSCTL6 &= ~(XT2OFF); // XT2 on

    UCSCTL6 |= XT2DRIVE0;
    UCSCTL6 &= ~XT2DRIVE1;

    SFRIFG1 &= ~OFIFG; // clear osc flag

    UCA0CTL1 = UCSWRST; // reset USCI 1

    UCA0CTL0 = 0x00;

    UCSCTL5 = 0x00; // ACLK, SMCLK source divider
    // 0 = dont divide ACK and SMCLK

    istate_t istate = __get_interrupt_state();
    __disable_interrupt(); // Disable global interrupts

    // orig 2100
    UCSCTL6 &= ~(XT1OFF); // XT1 on
    P7SEL |= 0x03; // Port select XT1
    UCSCTL6 |= XCAP_3; // ~ 12pF

    // UCSCTL6 |= (XT1OFF); // XT1 off
    P7SEL |= 0x03; // Port select XT1

    SFRIFG1 &= ~OFIFG; // clear osc flag

    UCSCTL3 = SELREF__XT2CLK |FLLREFDIV_4 ; // source for ffl is Xt2, div 4
    // output is DCO
    // 4 MHz div 4 = 16 MHz DCO


    UCSCTL4 = SELA__XT2CLK | SELS__DCOCLK | SELM__DCOCLK ; // ack clock source is xt2
    // source for mclk is DCO
    // source for smclk is DCO


    while(BAKCTL & LOCKIO) // unlock XT1
    BAKCTL &= ~(LOCKIO);


    do
    { // clear all osc, DCO flags
    UCSCTL7 &= ~ ( DCOFFG| XT1LFOFFG | XT1HFOFFG | XT2OFFG ); // **** I ALWAYS FAIL HERE **** OFIFG = 1
    SFRIFG1 &= ~OFIFG;
    } while(SFRIFG1 & OFIFG);


    UCSCTL1 |= DCORSEL_5; // MCLK = 16MHz(see 5xx6xx family usersguide p63)


    UCSCTL2 &= 0x0000;

    .
    .
    .


    ------------ my clock registers, per my debugger have the following values at this time I'm stuck in the loop

    UCSCTL0 = 0x1F00
    UCSCTL1 = 0x0020
    UCSCTL2 = 0x101F
    UCSCTL3 = 0x0054
    UCSCTL4 = 0x0533
    UCSCTL5 = 0x0000
    UCSCTL6 = 0x40CC
    UCSCTL7 = 0x0f11
    UCSCTL8 = 0x0707

    SFRIE1 = 0x000
    SFRIFG1 = 0x00C2
    SFRRPCR = 0x000C
  • 0 in reply to Dubs Mozz
    TI__Prodigy 335 points
    Good Morning Dubs,

    based on your UCS-Register dump it looks like your XT2 is up and running, because Bit3 in UCSCTL7 is not set, but Bit 0 is set and this means your DCO is in a fault state.
    Since you are use the DCO for SMCLK/MCLK and the XT2 divided by 4 as FLL-Reference you have to set the FLL-Divider and FLL-Multiplier (UCSCTL2) to suitable value. The formula to get those values is on page 164/165 in the user-guide SLAU208O.

    Actual your DCO runs with the default setting which are suppose to be used with a 32.768kHz Xtal as reference for the FLL. Using this setting with a much higher FLL-Reference -Clock, the FLL/DCO-Loop is not able to stabilized the resulting output frequency.

    I would suppose to use UCSCTL2 = 0x0010 (FLL-Divider div/1 and Multiplier x16) to achieve the 16 MHz DCO frequency based on your 4MHz input on XT2.

    Furthermore you have to select VCore-Level 2 at least to ensure proper device operation.

    Best regards,

    Michael

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