Maximum SPI Slaves, load capacitance?

Chetan said:

Does anyone here know how many 4 wire SPI slaves I can interface with MSP430 without a skew?

Without skew? - Impossible. There always will be some finite rise time, thus skew. No matter it is msp430 or modern high speed multigigabit i/o driver. So, you shall define what is maximum allowable skew for your application. At least you shall tell clock speed you are aiming at.

Your msp430 can drive 20pF load at 16 MHz speed.

The actual layout will have a significant influence. Not only parasitic capacities, but also on-matching line impedance (reflections) will reduce your possible clock frequency. Measuring might get troublesome, since most probes add another 10pF/1MOhm of load.

One can always scale down the clock frequency to get it work. Not sure if that breaks you application. In my experience, such high clock frequencies work only properly with line length in the range of a few centimeters.

16MHz @ 20pF is datasheet figure, not design spec. We are talking about 1MHz here

You cannot avoid testing your actual circuit with an oscilloscope, and choosing a frequency based on that.

There -do- exist good design tools that allow for a comprehensive simulation of the circuit (thermal and electrical). That would let you examine signal propagation properties, and catch grave design errors. Unfortunately, the pricing of those tools is usually beyond the hobbyists (or individual's) reach.

Additionally, keep in mind that an oscilloscope probe is already a significant load in this case. Perhaps the probe's HF settings (50 Ohm) would be more appropriate.

>but would expect this point not too far from 1MHz.
Do you recall old computers having PCI bus? Bus length on motherboards was at least few inches and bus ran at 33MHz. Indeed PCB trace impedance shall be matched and routing shall not be messed-up either, but please don't tell that 8*3pF is big problem at 1MHz, even at trace length that exceeds few cm - for output that is able to drive 20pF at 16MHz

... but please don't tell that 8*3pF is big problem at 1MHz, even at trace length that exceeds few cm - for output that is able to drive 20pF at 16MHz

Eight different slaves need to be placed at the PCB first - effective length for the capacitive load is the sum length. That's most probably more than a few centimeters.

... 8*3pF ...

Rather 8*30pF. BTW, load is the parasitic line capacity and the slave input capacity combined.

Remember that SPI signals are rectangular, and require, according to Fourier, a line bandwidth well into the VHF range to stay rectangular ...

f. m. said:

Rather 8*30pF. BTW, load is the parasitic line capacity and the slave input capacity combined.

I said: "40pF would be 10 I/Os having 3pF each and 10pF for trace capacitance." Note that 10pF equals 3 inches long 50 ohm transmission line on FR4

f. m. said:

Remember that SPI signals are rectangular

What a revelation.

f. m. said:

according to Fourier, a line bandwidth well into the VHF range to stay rectangular ...

This is so wrong to assume that SPI peripherals need strictly rectangular signal. Clock can look like sine and still follow all the specs and work without hitch, so in case of 1MHz it will be far from VHF.

This is so wrong to assume that SPI peripherals need strictly rectangular signal. Clock can look like sine and still follow all the specs and work without hitch, so in case of 1MHz it will be far from VHF.

When the formerly rectangular signal is reduced by bandwidth limitations to a quasi-sine, the probability of proper communication drops toward zero.