the difference of JTAG connection between msp432 Rev B and C

There are no differences between the JTAG connections of the MSP432P401R between rev B and C, but attached is the migration app report (SLAA700: www.ti.com/.../slaa700.pdf

However it is possible that the RevB device became corrupted after several programming attempts, in this instance a factory reset might be required. Instructions for factory resetting your MSP432 device are covered in the CCS 6.1 for MSP432 User's Guide (SLAU575): www.ti.com/.../slau575e.pdf

What specific error message are you receiving? Have you tried multiple RevB devices? It is worth noting that TI fully supports the RevC released silicon (as compared to RevB experimental silicon) and recommends that all customers exclusively use this revision for their products.

Regards,
Ryan

Ryan,

Thank you for your info.  We purchased the MCU directly from TI on 10-MAR-2016 with the lable: P/N: -XMS432P401RIPZR.  The chip surface is marked with Rev B.  The first time, it was OK.  Then flash download became unreliable.  We put the chip in a socket, so we may change the MCU in a few seconds without touching anything else.

We have tested a few MSP432 Rev B and a few Rev C.  Rev C always works with JTAG.  So far We have tested four Rev. B chips with flash download problems (See the screen capture above).  There are 5 more Rev B that are not used yet.  

We have tries many times.  What might be the problem that causes flash download failed?

Regards,

Glenn

You may want to take a look at this: processors.wiki.ti.com/.../XMS432_Support

i think i found out one reason : use flash loader in project or not(use IAR).

if i use the flash loader in project, the mcu of rev B can be success in first time but then failed.

but the mcu of Rev C has no problem of that.

i repeat the process in launchpad of black version.

so, how can i to solve this problem?

and the following is the debug log:

Mon Oct 31, 2016 15:03:48: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\TexasInstruments\MSP432P401R.dmac
Mon Oct 31, 2016 15:03:48: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\TexasInstruments\FlashMSP432P4.mac
Mon Oct 31, 2016 15:03:49: JLINK command: ProjectFile = D:\WorkingDir\Msp432\ucos_3rd\Micrium\Examples\TI\MSP-EXP432P401R\OS3\IAR\settings\OS3_Debug.jlink, return = 0
Mon Oct 31, 2016 15:03:49: JLINK command: scriptfile = C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\TexasInstruments\MSP432P4xx.JLinkScript, return = 0
Mon Oct 31, 2016 15:03:49: Device "MSP432P401R" selected.
Mon Oct 31, 2016 15:03:49: DLL version: V5.2c, compiled Sep 10 2015 17:39:31
Mon Oct 31, 2016 15:03:49: Firmware: J-Link V9 compiled Sep 18 2015 19:53:12
Mon Oct 31, 2016 15:03:49: Selecting SWD as current target interface.
Mon Oct 31, 2016 15:03:49: JTAG speed is initially set to: 12000 kHz
Mon Oct 31, 2016 15:03:49: ******************************
Mon Oct 31, 2016 15:03:49: * J-Link script: MSP432P401R *
Mon Oct 31, 2016 15:03:49: ******************************
Mon Oct 31, 2016 15:03:49: CPUID register: 0x410FC241
Mon Oct 31, 2016 15:03:49: Found SWD-DP with ID 0x2BA01477
Mon Oct 31, 2016 15:03:49: SWD speed too high. Reduced from 12000 kHz to 3416 kHz for stability
Mon Oct 31, 2016 15:03:49: Found Cortex-M4 r0p1, Little endian.
Mon Oct 31, 2016 15:03:49: FPUnit: 6 code (BP) slots and 2 literal slots
Mon Oct 31, 2016 15:03:49: CoreSight components:
Mon Oct 31, 2016 15:03:49: ROMTbl 0 @ E00FF000
Mon Oct 31, 2016 15:03:49: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Mon Oct 31, 2016 15:03:49: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Mon Oct 31, 2016 15:03:49: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Mon Oct 31, 2016 15:03:49: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Mon Oct 31, 2016 15:03:49: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Mon Oct 31, 2016 15:03:49: Hardware reset with strategy 0 was performed
Mon Oct 31, 2016 15:03:49: Initial reset was performed
Mon Oct 31, 2016 15:03:49: Resetting device to restore clock configuration
Mon Oct 31, 2016 15:03:49: Hardware reset with strategy 1 was performed
Mon Oct 31, 2016 15:03:49: Halting watchdog timer
Mon Oct 31, 2016 15:03:49: Clearing PCM_CTL LOCK_SD and LOCK_RTC bits
Mon Oct 31, 2016 15:03:49: Enabling all SRAM banks
Mon Oct 31, 2016 15:03:49: 2560 bytes downloaded (22.94 Kbytes/sec)
Mon Oct 31, 2016 15:03:49: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\TexasInstruments\FlashMSP432P4.out
Mon Oct 31, 2016 15:03:49: Target reset
Mon Oct 31, 2016 15:03:56: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\TexasInstruments\FlashMSP432P4.mac

The debug log does recommend that you decrease the SWD speed, has this been attempted?

Regards,
Ryan