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XT2 / 3 frequency (50% duty cycle) on MSP430F5510 pin output

zrno soli
Guru 34313 points
Other Parts Discussed in Thread: MSP430F5510

Few years ago my conclusion was that it is not possible to have frequency from XT2 (24 MHz) divided by 3 (8 MHz, 50% duty cycle) on (MSP430F5510) port pin as output. Now, I am back to this topic again, and I am sure that this can't be done.

Timers (50% duty cycle) / ACLK / SMCLK output can be XT2 divided by 2, 4, 8... not by 3. However, ADC10DIVx (ADC10CLK output) can be divided by 1, 2, 3, 4... and even in family datasheet ADC clock is presented as 50% duty cycle, it is not. On picture is (XT2 24 MHz) divided by 8, measured frequency is 3, but on logic analyzer it is not signal with 50% duty cycle.

  • 0
    Guru 268780 points
    You can configure a timer to set/reset an output after three/six ticks.
  • 0
    Guru 46710 points

    zrno soli said:
    even in family datasheet ADC clock is presented as 50% duty cycle

    Perhaps 50% duty clock is shown in figures, but 50% duty cycle is *not* mentioned in ADC Timing Parameters next to max 5.5MHz fADC10CLK.

    Sure - whole chip and its peripherals *requires* 50% duty clock - at max fSYSTEM (25 MHz). This is kinda obscure way to tell that clock pulse shall not be shorter than 20ns. Would be nice to hear TI "official" comment on this.

  • 0 in reply to Clemens Ladisch
    Guru 34313 points

    Clemens Ladisch said:
    You can configure a timer to set/reset an output after three/six ticks.

    Yes, but this will give 24 MHz / 6 = 4 MHz output, not 8 MHz.

  • 0 in reply to zrno soli
    Guru 268780 points
    Oops.

    Hmm, dividing by three requires that the circuit acts on the 'wrong' edge of the clock. I guess this is not possible without external logic.
  • 0 in reply to zrno soli
    Guru 34313 points

    There are is really nice, detail description (no doubts of any kind) for USCI clock inside slau208 5xx / 6xx family datasheet (37.3.6 Serial Clock Control).

    Even UCBRx settings result in even divisions and, thus, generate a bit clock with a 50/50 duty cycle.

    Odd UCBRx settings result in odd divisions. In this case, the high phase of the bit clock is one BRCLK
    cycle longer than the low phase.

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