Problem with Keil + PWM at EK-TM4C123GXL LaunchPad

// PWMDual.c
// Runs on TM4C123
// Use PWM0/PB6 and PWM1/PB7 to generate two square waves with 50% duty cycle
// and 180 degrees out of phase.
// Daniel Valvano
// September 10, 2013

/* This example accompanies the book
   "Embedded Systems: Real Time Interfacing to ARM Cortex M Microcontrollers",
   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013
  Program 6.7, section 6.3.2

 Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
    You may use, edit, run or distribute this file
    as long as the above copyright notice remains
 THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 For more information about my classes, my research, and my books, see
 http://users.ece.utexas.edu/~valvano/
 */

#define PWM0_ENABLE_R           (*((volatile unsigned long *)0x40028008))
#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
#define PWM0_0_CTL_R            (*((volatile unsigned long *)0x40028040))
#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
#define PWM_0_CTL_ENABLE        0x00000001  // PWM Block Enable
#define PWM0_0_LOAD_R           (*((volatile unsigned long *)0x40028050))
#define PWM0_0_CMPA_R           (*((volatile unsigned long *)0x40028058))
#define PWM0_0_CMPB_R           (*((volatile unsigned long *)0x4002805C))
#define PWM0_0_GENA_R           (*((volatile unsigned long *)0x40028060))
#define PWM_0_GENA_ACTCMPBD_ZERO 0x00000800  // Set the output signal to 0
#define PWM_0_GENA_ACTCMPBU_ONE  0x00000300  // Set the output signal to 1
#define PWM0_0_GENB_R           (*((volatile unsigned long *)0x40028064))
#define PWM_0_GENB_ACTCMPAD_ZERO                                              \
                                0x00000080  // Set the output signal to 0
#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1
#define GPIO_PORTB_AFSEL_R      (*((volatile unsigned long *)0x40005420))
#define GPIO_PORTB_DEN_R        (*((volatile unsigned long *)0x4000551C))
#define GPIO_PORTB_AMSEL_R      (*((volatile unsigned long *)0x40005528))
#define GPIO_PORTB_PCTL_R       (*((volatile unsigned long *)0x4000552C))
#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
#define SYSCTL_RCGC0_R          (*((volatile unsigned long *)0x400FE100))
#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control

// period is 16-bit number of PWM clock cycles in one period (3<=period)
// PWM clock rate = processor clock rate/SYSCTL_RCC_PWMDIV
//                = BusClock/64 
//                = 3.2 MHz/64 = 50 kHz (in this example)
void PWM0Dual_Init(unsigned long period, unsigned short dcpwm0,  unsigned short dcpwm1){
  volatile unsigned long delay;
  SYSCTL_RCGC0_R |= SYSCTL_RCGC0_PWM0;  // 1) activate PWM0
  SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOB; // 2) activate port B
  delay = SYSCTL_RCGC2_R;               // allow time to finish activating
  GPIO_PORTB_AFSEL_R |= 0xC0;           // enable alt funct on PB7-6
  GPIO_PORTB_PCTL_R &= ~0xFF000000;     // configure PB7-6 as PWM0
  GPIO_PORTB_PCTL_R |= 0x44000000;
  GPIO_PORTB_AMSEL_R &= ~0xC0;          // disable analog functionality on PB7-6
  GPIO_PORTB_DEN_R |= 0xC0;             // enable digital I/O on PB7-6
  SYSCTL_RCC_R |= SYSCTL_RCC_USEPWMDIV; // 3) use PWM divider
  SYSCTL_RCC_R &= ~SYSCTL_RCC_PWMDIV_M; //    clear PWM divider field
  SYSCTL_RCC_R += SYSCTL_RCC_PWMDIV_64; //    configure for /64 divider
  PWM0_0_CTL_R = 0;                     // 4) disable PWM while initializing
  //PWM0, Generator B (PWM0/PB6) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM0_0_GENA_R = (PWM_0_GENA_ACTCMPBD_ZERO|PWM_0_GENA_ACTCMPBU_ONE);
  //PWM0, Generator B (PWM1/PB7) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM0_0_GENB_R = (PWM_0_GENB_ACTCMPAD_ZERO|PWM_0_GENB_ACTCMPAU_ONE);
  PWM0_0_LOAD_R = (period - 1)/2;       // 5) count from zero to this number and back to zero in (period - 1) cycles
  PWM0_0_CMPA_R = (period*dcpwm1)/100;       // 6) count value when PWM1/PB7 toggles
  PWM0_0_CMPB_R = (period*dcpwm0)/100;       // 6) count value when PWM1/PB7 toggles
                                        // 7) start PWM0 in Count Up/Down mode
  PWM0_0_CTL_R |= (PWM_0_CTL_MODE|PWM_0_CTL_ENABLE);
                                        // enable PWM1-0
  PWM0_ENABLE_R |= (PWM_ENABLE_PWM1EN|PWM_ENABLE_PWM0EN);
}
// change period
// period is 16-bit number of PWM clock cycles in one period (3<=period)
void PWM0Dual_Period(unsigned short dcpwm0, unsigned short dcpwm1){
	unsigned long period;
	period = PWM0_0_LOAD_R;
  PWM0_0_CMPA_R = (period*(101-dcpwm1))/100;       // 8) count value when PWM1/PB7 toggles
  PWM0_0_CMPB_R = (period*(65536-dcpwm0))/65535;       // 9) count value when PWM0/PB6 toggles
}

// PWMDual1.c
// Runs on TM4C123
// Use PWM0/PB6 and PWM1/PB7 to generate two square waves with 50% duty cycle
// and 180 degrees out of phase.
// Daniel Valvano
// September 10, 2013

// Please note:
/*
   This is a modified version from original Jonathan Valvano's routine
	 
	 This is an example routine I prepared to handle a hobby servo motor 
	 by PWM tested with a EK-TM4C123GXL board TM4C123.
	 Connections are:
	 PD0 is for PWM input on servo motor
	 Tested with a standard Tower Pro MG90S Micro servo motor
	 where 20 milliseconds is the standard period for the PWM input
	 0.9 ms is for +90� position
	 1.65 ms is for 0� position
	 2.4 ms is for -90 � position
	 by Francisco Dominguez Roman 2014 Twitter: @Franciscodr
	 blog http://www.gestionconsult.es/blog/
	 more information of robotics at http://letsmakerobots.com/content/lets-learn-basics-robotics-edxs-embedded-systems-shape-world
	 and http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/342633/1201161.aspx

*/ 

/* This example accompanies the book
   "Embedded Systems: Real Time Interfacing to ARM Cortex M Microcontrollers",
   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013
  Program 6.7, section 6.3.2

 Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
    You may use, edit, run or distribute this file
    as long as the above copyright notice remains
 THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 For more information about my classes, my research, and my books, see
 http://users.ece.utexas.edu/~valvano/
 */

#define PWM1_ENABLE_R           (*((volatile unsigned long *)0x40029008))
#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
#define PWM1_0_CTL_R            (*((volatile unsigned long *)0x40029040))
#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
#define PWM1_0_LOAD_R           (*((volatile unsigned long *)0x40029050))
#define PWM1_0_CMPA_R           (*((volatile unsigned long *)0x40029058))
#define PWM1_0_CMPB_R           (*((volatile unsigned long *)0x4002905C))
#define PWM1_0_GENA_R           (*((volatile unsigned long *)0x40029060))
#define PWM_1_GENA_ACTCMPBD_ZERO 0x00000800  // Set the output signal to 0
#define PWM_1_GENA_ACTCMPBU_ONE  0x00000300  // Set the output signal to 1
#define PWM1_0_GENB_R           (*((volatile unsigned long *)0x40029064))
#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
                                0x00000080  // Set the output signal to 0
#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1
#define GPIO_PORTD_AFSEL_R      (*((volatile unsigned long *)0x40007420))
#define GPIO_PORTD_DEN_R        (*((volatile unsigned long *)0x4000751C))
#define GPIO_PORTD_AMSEL_R      (*((volatile unsigned long *)0x40007528))
#define GPIO_PORTD_PCTL_R       (*((volatile unsigned long *)0x4000752C))
#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
#define SYSCTL_RCGC0_R          (*((volatile unsigned long *)0x400FE100))
#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
//#define PWM0_1_GENA_R           (*((volatile unsigned long *)0x400280A0))


// period is 16-bit number of PWM clock cycles in one period (3<=period)
// PWM clock rate = processor clock rate/SYSCTL_RCC_PWMDIV
//                = BusClock/64 
//                = 3.2 MHz/64 = 50 kHz (in this example)
void PWM1Dual_Init(unsigned long period2, unsigned short dcpwm2,  unsigned short dcpwm3){
  volatile unsigned long delay;
  SYSCTL_RCGC0_R |= SYSCTL_RCGC0_PWM0;  // 1) activate PWM1
  SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOD; // 2) activate port D
  delay = SYSCTL_RCGC2_R;               // allow time to finish activating
  GPIO_PORTD_AFSEL_R |= 0x03;           // enable alt funct on PD1-0
  GPIO_PORTD_PCTL_R &= ~0x000000FF;     // configure PD2-1 as PWM1
  GPIO_PORTD_PCTL_R |= 0x44000000;
  GPIO_PORTD_AMSEL_R &= ~0x03;          // disable analog functionality on PD1-0
  GPIO_PORTD_DEN_R |= 0x03;             // enable digital I/O on PD1-0
  SYSCTL_RCC_R |= SYSCTL_RCC_USEPWMDIV; // 3) use PWM divider
  SYSCTL_RCC_R &= ~SYSCTL_RCC_PWMDIV_M; //    clear PWM divider field
  SYSCTL_RCC_R += SYSCTL_RCC_PWMDIV_64; //    configure for /64 divider
  PWM1_0_CTL_R = 0;                     // 4) disable PWM while initializing
  //PWM0, Generator B (PWM0/PB6) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENA_R = (PWM_1_GENA_ACTCMPBD_ZERO|PWM_1_GENA_ACTCMPBU_ONE);
  //PWM0, Generator B (PWM1/PB7) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENB_R = (PWM_1_GENB_ACTCMPAD_ZERO|PWM_1_GENB_ACTCMPAU_ONE);
  PWM1_0_LOAD_R = (period2 - 1)/2;       // 5) count from zero to this number and back to zero in (period - 1) cycles
  PWM1_0_CMPA_R = (period2*dcpwm3)/100;       // 6) count value when PWM1/PD0 toggles
  PWM1_0_CMPB_R = (period2*dcpwm2)/100;       // 6) count value when PWM1/PD1 toggles
                                        // 7) start PWM0 in Count Up/Down mode
  PWM1_0_CTL_R |= (PWM_0_CTL_MODE|PWM_1_CTL_ENABLE);
                                        // enable PWM1-0
  PWM1_ENABLE_R |= (PWM_ENABLE_PWM3EN|PWM_ENABLE_PWM3EN);
}
// change period
// period is 16-bit number of PWM clock cycles in one period (3<=period)
void PWM1Dual_Period(unsigned short dcpwm2, unsigned short dcpwm3){
	unsigned long period2;
	period2 = PWM1_0_LOAD_R;
  PWM1_0_CMPA_R = (period2*(101-dcpwm3))/100;       // 8) count value when PWM1/PD1 toggles
  PWM1_0_CMPB_R = (period2*(65536-dcpwm2))/65535;       // 9) count value when PWM0/PD0 toggles
}

// PWMDual1.c
// Runs on TM4C123
// Use PWM0/PB6 and PWM1/PB7 to generate two square waves with 50% duty cycle
// and 180 degrees out of phase.
// Daniel Valvano
// September 10, 2013

// Please note:
/*
   This is a modified version from original Jonathan Valvano's routine
	 
	 This is an example routine I prepared to handle a hobby servo motor 
	 by PWM tested with a EK-TM4C123GXL board TM4C123.
	 Connections are:
	 PD0 is for PWM input on servo motor
	 Tested with a standard Tower Pro MG90S Micro servo motor
	 where 20 milliseconds is the standard period for the PWM input
	 0.9 ms is for +90� position
	 1.65 ms is for 0� position
	 2.4 ms is for -90 � position
	 by Francisco Dominguez Roman 2014 Twitter: @Franciscodr
	 blog http://www.gestionconsult.es/blog/
	 more information of robotics at http://letsmakerobots.com/content/lets-learn-basics-robotics-edxs-embedded-systems-shape-world
	 and http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/342633/1201161.aspx

*/ 

/* This example accompanies the book
   "Embedded Systems: Real Time Interfacing to ARM Cortex M Microcontrollers",
   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013
  Program 6.7, section 6.3.2

 Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
    You may use, edit, run or distribute this file
    as long as the above copyright notice remains
 THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 For more information about my classes, my research, and my books, see
 http://users.ece.utexas.edu/~valvano/
 */

#define PWM1_ENABLE_R           (*((volatile unsigned long *)0x40029008))
#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
#define PWM1_0_CTL_R            (*((volatile unsigned long *)0x40029040))
#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
#define PWM1_0_LOAD_R           (*((volatile unsigned long *)0x40029050))
#define PWM1_0_CMPA_R           (*((volatile unsigned long *)0x40029058))
#define PWM1_0_CMPB_R           (*((volatile unsigned long *)0x4002905C))
#define PWM1_0_GENA_R           (*((volatile unsigned long *)0x40029060))
#define PWM_1_GENA_ACTCMPBD_ZERO 0x00000800  // Set the output signal to 0
#define PWM_1_GENA_ACTCMPBU_ONE  0x00000300  // Set the output signal to 1
#define PWM1_0_GENB_R           (*((volatile unsigned long *)0x40029064))
#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
                                0x00000080  // Set the output signal to 0
#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1
#define GPIO_PORTD_AFSEL_R      (*((volatile unsigned long *)0x40007420))
#define GPIO_PORTD_DEN_R        (*((volatile unsigned long *)0x4000751C))
#define GPIO_PORTD_AMSEL_R      (*((volatile unsigned long *)0x40007528))
#define GPIO_PORTD_PCTL_R       (*((volatile unsigned long *)0x4000752C))
#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
#define SYSCTL_RCGC0_R          (*((volatile unsigned long *)0x400FE100))
#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
//#define PWM0_1_GENA_R           (*((volatile unsigned long *)0x400280A0))
#define SYSCTL_RCGC_PWM_R          (*((volatile unsigned long *)0x400FE640))
#define SYSCTL_RCGC_PWM       0x00000002  // PWM Clock Gating Control

// period is 16-bit number of PWM clock cycles in one period (3<=period)
// PWM clock rate = processor clock rate/SYSCTL_RCC_PWMDIV
//                = BusClock/64 
//                = 3.2 MHz/64 = 50 kHz (in this example)
void PWM1Dual_Init(unsigned long period2, unsigned short dcpwm2,  unsigned short dcpwm3){
  volatile unsigned long delay;
  SYSCTL_RCGC_PWM_R  |= SYSCTL_RCGC_PWM;  // 1) activate PWM1
  SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOD; // 2) activate port D
  delay = SYSCTL_RCGC2_R;               // allow time to finish activating
  GPIO_PORTD_AFSEL_R |= 0x03;           // enable alt funct on PD1-0
  GPIO_PORTD_PCTL_R &= ~0x00000055;     // configure PD2-1 as PWM1
  GPIO_PORTD_PCTL_R |= 0x44000000;
  GPIO_PORTD_AMSEL_R &= ~0x03;          // disable analog functionality on PD1-0
  GPIO_PORTD_DEN_R |= 0x03;             // enable digital I/O on PD1-0
  SYSCTL_RCC_R |= SYSCTL_RCC_USEPWMDIV; // 3) use PWM divider
  SYSCTL_RCC_R &= ~SYSCTL_RCC_PWMDIV_M; //    clear PWM divider field
  SYSCTL_RCC_R += SYSCTL_RCC_PWMDIV_64; //    configure for /64 divider
  PWM1_0_CTL_R = 0;                     // 4) disable PWM while initializing
  //PWM0, Generator B (PWM0/PB6) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENA_R = (PWM_1_GENA_ACTCMPBD_ZERO|PWM_1_GENA_ACTCMPBU_ONE);
  //PWM0, Generator B (PWM1/PB7) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENB_R = (PWM_1_GENB_ACTCMPAD_ZERO|PWM_1_GENB_ACTCMPAU_ONE);
  PWM1_0_LOAD_R = (period2 - 1)/2;       // 5) count from zero to this number and back to zero in (period - 1) cycles
  PWM1_0_CMPA_R = (period2*dcpwm3)/100;       // 6) count value when PWM1/PD0 toggles
  PWM1_0_CMPB_R = (period2*dcpwm2)/100;       // 6) count value when PWM1/PD1 toggles
                                        // 7) start PWM0 in Count Up/Down mode
  PWM1_0_CTL_R |= (PWM_0_CTL_MODE|PWM_1_CTL_ENABLE);
                                        // enable PWM1-0
  PWM1_ENABLE_R |= (PWM_ENABLE_PWM3EN|PWM_ENABLE_PWM3EN);
}
// change period
// period is 16-bit number of PWM clock cycles in one period (3<=period)
void PWM1Dual_Period(unsigned short dcpwm2, unsigned short dcpwm3){
	unsigned long period2;
	period2 = PWM1_0_LOAD_R;
  PWM1_0_CMPA_R = (period2*(101-dcpwm3))/100;       // 8) count value when PWM1/PD1 toggles
  PWM1_0_CMPB_R = (period2*(65536-dcpwm2))/65535;       // 9) count value when PWM0/PD0 toggles
}

// PWMDual1.c
// Runs on TM4C123
// Use PWM0/PB6 and PWM1/PB7 to generate two square waves with 50% duty cycle
// and 180 degrees out of phase.
// Daniel Valvano
// September 10, 2013

// Please note:
/*
   This is a modified version from original Jonathan Valvano's routine
	 
	 This is an example routine I prepared to handle a hobby servo motor 
	 by PWM tested with a EK-TM4C123GXL board TM4C123.
	 Connections are:
	 PD0 is for PWM input on servo motor
	 Tested with a standard Tower Pro MG90S Micro servo motor
	 where 20 milliseconds is the standard period for the PWM input
	 0.9 ms is for +90� position
	 1.65 ms is for 0� position
	 2.4 ms is for -90 � position
	 by Francisco Dominguez Roman 2014 Twitter: @Franciscodr
	 blog http://www.gestionconsult.es/blog/
	 more information of robotics at http://letsmakerobots.com/content/lets-learn-basics-robotics-edxs-embedded-systems-shape-world
	 and http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/342633/1201161.aspx

*/ 

/* This example accompanies the book
   "Embedded Systems: Real Time Interfacing to ARM Cortex M Microcontrollers",
   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013
  Program 6.7, section 6.3.2

 Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
    You may use, edit, run or distribute this file
    as long as the above copyright notice remains
 THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 For more information about my classes, my research, and my books, see
 http://users.ece.utexas.edu/~valvano/
 */

#define PWM1_ENABLE_R           (*((volatile unsigned long *)0x40029008))
#define PWM_ENABLE_PWM3EN       0x00000002  // PWM1 Output Enable
#define PWM_ENABLE_PWM2EN       0x00000001  // PWM0 Output Enable
#define PWM1_0_CTL_R            (*((volatile unsigned long *)0x40029040))
#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
#define PWM1_0_LOAD_R           (*((volatile unsigned long *)0x40029050))
#define PWM1_0_CMPA_R           (*((volatile unsigned long *)0x40029058))
#define PWM1_0_CMPB_R           (*((volatile unsigned long *)0x4002905C))
#define PWM1_0_GENA_R           (*((volatile unsigned long *)0x40029060))
#define PWM_1_GENA_ACTCMPBD_ZERO 0x00000800  // Set the output signal to 0
#define PWM_1_GENA_ACTCMPBU_ONE  0x00000300  // Set the output signal to 1
#define PWM1_0_GENB_R           (*((volatile unsigned long *)0x40029064))
#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
                                0x00000080  // Set the output signal to 0
#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1
#define GPIO_PORTD_AFSEL_R      (*((volatile unsigned long *)0x40007420))
#define GPIO_PORTD_DEN_R        (*((volatile unsigned long *)0x4000751C))
#define GPIO_PORTD_AMSEL_R      (*((volatile unsigned long *)0x40007528))
#define GPIO_PORTD_PCTL_R       (*((volatile unsigned long *)0x4000752C))
#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
#define SYSCTL_RCGC0_R          (*((volatile unsigned long *)0x400FE100))
#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
//#define PWM0_1_GENA_R           (*((volatile unsigned long *)0x400280A0))
#define SYSCTL_RCGC_PWM_R          (*((volatile unsigned long *)0x400FE640))
#define SYSCTL_RCGC_PWM       0x00000002  // PWM Clock Gating Control

// period is 16-bit number of PWM clock cycles in one period (3<=period)
// PWM clock rate = processor clock rate/SYSCTL_RCC_PWMDIV
//                = BusClock/64 
//                = 3.2 MHz/64 = 50 kHz (in this example)
void PWM1Dual_Init(unsigned long period2, unsigned short dcpwm2,  unsigned short dcpwm3){
  volatile unsigned long delay;
  SYSCTL_RCGC_PWM_R  |= SYSCTL_RCGC_PWM;  // 1) activate PWM1
  SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOD; // 2) activate port D
  delay = SYSCTL_RCGC2_R;               // allow time to finish activating
  GPIO_PORTD_AFSEL_R |= 0x03;           // enable alt funct on PD1-0
  GPIO_PORTD_PCTL_R &= ~0x000000FF;     // configure PD1-0 as PWM1
  GPIO_PORTD_PCTL_R |= 0x00000055;
  GPIO_PORTD_AMSEL_R &= ~0x03;          // disable analog functionality on PD1-0
  GPIO_PORTD_DEN_R |= 0x03;             // enable digital I/O on PD1-0
  SYSCTL_RCC_R |= SYSCTL_RCC_USEPWMDIV; // 3) use PWM divider
  SYSCTL_RCC_R &= ~SYSCTL_RCC_PWMDIV_M; //    clear PWM divider field
  SYSCTL_RCC_R += SYSCTL_RCC_PWMDIV_64; //    configure for /64 divider
  PWM1_0_CTL_R = 0;                     // 4) disable PWM while initializing
  //PWM0, Generator B (PWM0/PB6) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENA_R = (PWM_1_GENA_ACTCMPBD_ZERO|PWM_1_GENA_ACTCMPBU_ONE);
  //PWM0, Generator B (PWM1/PB7) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENB_R = (PWM_1_GENB_ACTCMPAD_ZERO|PWM_1_GENB_ACTCMPAU_ONE);
  PWM1_0_LOAD_R = (period2 - 1)/2;       // 5) count from zero to this number and back to zero in (period - 1) cycles
  PWM1_0_CMPA_R = (period2*dcpwm3)/100;       // 6) count value when PWM1/PD0 toggles
  PWM1_0_CMPB_R = (period2*dcpwm2)/100;       // 6) count value when PWM1/PD1 toggles
                                        // 7) start PWM0 in Count Up/Down mode
  PWM1_0_CTL_R |= (PWM_0_CTL_MODE|PWM_1_CTL_ENABLE);
                                        // enable PWM1-0
  PWM1_ENABLE_R |= (PWM_ENABLE_PWM1EN|PWM_ENABLE_PWM0EN);
}
// change period
// period is 16-bit number of PWM clock cycles in one period (3<=period)
void PWM1Dual_Period(unsigned short dcpwm2, unsigned short dcpwm3){
	unsigned long period2;
	period2 = PWM1_0_LOAD_R;
  PWM1_0_CMPA_R = (period2*(101-dcpwm3))/100;       // 8) count value when PWM1/PD1 toggles
  PWM1_0_CMPB_R = (period2*(65536-dcpwm2))/65535;       // 9) count value when PWM0/PD0 toggles
}

// PWMDual1.c
// Runs on TM4C123
// Use PWM0/PB6 and PWM1/PB7 to generate two square waves with 50% duty cycle
// and 180 degrees out of phase.
// Daniel Valvano
// September 10, 2013

// Please note:
/*
   This is a modified version from original Jonathan Valvano's routine
	 
	 This is an example routine I prepared to handle a hobby servo motor 
	 by PWM tested with a EK-TM4C123GXL board TM4C123.
	 Connections are:
	 PD0 is for PWM input on servo motor
	 Tested with a standard Tower Pro MG90S Micro servo motor
	 where 20 milliseconds is the standard period for the PWM input
	 0.9 ms is for +90� position
	 1.65 ms is for 0� position
	 2.4 ms is for -90 � position
	 by Francisco Dominguez Roman 2014 Twitter: @Franciscodr
	 blog http://www.gestionconsult.es/blog/
	 more information of robotics at http://letsmakerobots.com/content/lets-learn-basics-robotics-edxs-embedded-systems-shape-world
	 and http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/342633/1201161.aspx

*/ 

/* This example accompanies the book
   "Embedded Systems: Real Time Interfacing to ARM Cortex M Microcontrollers",
   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013
  Program 6.7, section 6.3.2

 Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
    You may use, edit, run or distribute this file
    as long as the above copyright notice remains
 THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 For more information about my classes, my research, and my books, see
 http://users.ece.utexas.edu/~valvano/
 */

#define PWM1_ENABLE_R           (*((volatile unsigned long *)0x40029008))
#define PWM_ENABLE_PWM3EN       0x00000002  // PWM1 Output Enable
#define PWM_ENABLE_PWM2EN       0x00000001  // PWM0 Output Enable
#define PWM1_0_CTL_R            (*((volatile unsigned long *)0x40029040))
#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
#define PWM1_0_LOAD_R           (*((volatile unsigned long *)0x40029050))
#define PWM1_0_CMPA_R           (*((volatile unsigned long *)0x40029058))
#define PWM1_0_CMPB_R           (*((volatile unsigned long *)0x4002905C))
#define PWM1_0_GENA_R           (*((volatile unsigned long *)0x40029060))
#define PWM_1_GENA_ACTCMPBD_ZERO 0x00000800  // Set the output signal to 0
#define PWM_1_GENA_ACTCMPBU_ONE  0x00000300  // Set the output signal to 1
#define PWM1_0_GENB_R           (*((volatile unsigned long *)0x40029064))
#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
                                0x00000080  // Set the output signal to 0
#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1
#define GPIO_PORTD_AFSEL_R      (*((volatile unsigned long *)0x40007420))
#define GPIO_PORTD_DEN_R        (*((volatile unsigned long *)0x4000751C))
#define GPIO_PORTD_AMSEL_R      (*((volatile unsigned long *)0x40007528))
#define GPIO_PORTD_PCTL_R       (*((volatile unsigned long *)0x4000752C))
#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
#define SYSCTL_RCGC0_R          (*((volatile unsigned long *)0x400FE100))
#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
//#define PWM0_1_GENA_R           (*((volatile unsigned long *)0x400280A0))
#define SYSCTL_RCGC_PWM_R          (*((volatile unsigned long *)0x400FE640))
// #define SYSCTL_RCGC_PWM       0x00000002  // PWM Clock Gating Control (WRONG ONE)
#define SYSCTL_RCGC_PWM0       0x00000001  // PWM Clock Gating Control


// period is 16-bit number of PWM clock cycles in one period (3<=period)
// PWM clock rate = processor clock rate/SYSCTL_RCC_PWMDIV
//                = BusClock/64 
//                = 3.2 MHz/64 = 50 kHz (in this example)
void PWM1Dual_Init(unsigned long period2, unsigned short dcpwm2,  unsigned short dcpwm3){
  volatile unsigned long delay;
//  SYSCTL_RCGC_PWM_R  |= SYSCTL_RCGC_PWM;  // 1) activate PWM1 (WRONG ONE)
//  SYSCTL_RCGC_PWM_R  |= SYSCTL_RCGC_PWM0;  // 1) activate PWM1 

  SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOD; // 2) activate port D
  delay = SYSCTL_RCGC2_R;               // allow time to finish activating
  GPIO_PORTD_AFSEL_R |= 0x03;           // enable alt funct on PD1-0
  GPIO_PORTD_PCTL_R &= ~0x000000FF;     // configure PD1-0 as PWM1
  GPIO_PORTD_PCTL_R |= 0x00000055;
  GPIO_PORTD_AMSEL_R &= ~0x03;          // disable analog functionality on PD1-0
  GPIO_PORTD_DEN_R |= 0x03;             // enable digital I/O on PD1-0
  SYSCTL_RCC_R |= SYSCTL_RCC_USEPWMDIV; // 3) use PWM divider
  SYSCTL_RCC_R &= ~SYSCTL_RCC_PWMDIV_M; //    clear PWM divider field
  SYSCTL_RCC_R += SYSCTL_RCC_PWMDIV_64; //    configure for /64 divider
  PWM1_0_CTL_R = 0;                     // 4) disable PWM while initializing
  //PWM0, Generator B (PWM0/PB6) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENA_R = (PWM_1_GENA_ACTCMPBD_ZERO|PWM_1_GENA_ACTCMPBU_ONE);
  //PWM0, Generator B (PWM1/PB7) goes to 0 when count==CMPA counting down and 1 when count==CMPA counting up
  PWM1_0_GENB_R = (PWM_1_GENB_ACTCMPAD_ZERO|PWM_1_GENB_ACTCMPAU_ONE);
  PWM1_0_LOAD_R = (period2 - 1)/2;       // 5) count from zero to this number and back to zero in (period - 1) cycles
  PWM1_0_CMPA_R = (period2*dcpwm3)/100;       // 6) count value when PWM1/PD0 toggles
  PWM1_0_CMPB_R = (period2*dcpwm2)/100;       // 6) count value when PWM1/PD1 toggles
                                        // 7) start PWM0 in Count Up/Down mode
  PWM1_0_CTL_R |= (PWM_0_CTL_MODE|PWM_1_CTL_ENABLE);
                                        // enable PWM1-0
  PWM1_ENABLE_R |= (PWM_ENABLE_PWM1EN|PWM_ENABLE_PWM0EN);
}
// change period
// period is 16-bit number of PWM clock cycles in one period (3<=period)
void PWM1Dual_Period(unsigned short dcpwm2, unsigned short dcpwm3){
	unsigned long period2;
	period2 = PWM1_0_LOAD_R;
  PWM1_0_CMPA_R = (period2*(101-dcpwm3))/100;       // 8) count value when PWM1/PD1 toggles
  PWM1_0_CMPB_R = (period2*(65536-dcpwm2))/65535;       // 9) count value when PWM0/PD0 toggles
}

// Nokia5110.c
// Runs on LM4F120/TM4C123
// Use SSI0 to send an 8-bit code to the Nokia5110 48x84
// pixel LCD to display text, images, or other information.
// This file has been modified to work with TExaS, which
// sets the PLL to 80 MHz, where earlier versions ran at
// 50 MHz or less.
// Daniel Valvano
// December 10, 2013

// Font table, initialization, and other functions based
// off of Nokia_5110_Example from Spark Fun:
// 7-17-2011
// Spark Fun Electronics 2011
// Nathan Seidle
// http://dlnmh9ip6v2uc.cloudfront.net/datasheets/LCD/Monochrome/Nokia_5110_Example.pde

/* This example accompanies the book
   "Embedded Systems: Real Time Interfacing to Arm Cortex M Microcontrollers",
   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013

 Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
    You may use, edit, run or distribute this file
    as long as the above copyright notice remains
 THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 For more information about my classes, my research, and my books, see
 http://users.ece.utexas.edu/~valvano/
 */

// Blue Nokia 5110
// ---------------
// Signal        (Nokia 5110) LaunchPad pin
// Reset         (RST, pin 1) connected to PA7
// SSI0Fss       (CE,  pin 2) connected to PA3
// Data/Command  (DC,  pin 3) connected to PA6
// SSI0Tx        (Din, pin 4) connected to PA5
// SSI0Clk       (Clk, pin 5) connected to PA2
// 3.3V          (Vcc, pin 6) power
// back light    (BL,  pin 7) not connected, consists of 4 white LEDs which draw ~80mA total
// Ground        (Gnd, pin 8) ground

// Red SparkFun Nokia 5110 (LCD-10168)
// -----------------------------------
// Signal        (Nokia 5110) LaunchPad pin
// 3.3V          (VCC, pin 1) power
// Ground        (GND, pin 2) ground
// SSI0Fss       (SCE, pin 3) connected to PA3
// Reset         (RST, pin 4) connected to PA7
// Data/Command  (D/C, pin 5) connected to PA6
// SSI0Tx        (DN,  pin 6) connected to PA5
// SSI0Clk       (SCLK, pin 7) connected to PA2
// back light    (LED, pin 8) not connected, consists of 4 white LEDs which draw ~80mA total

#include "Nokia5110.h"
// Maximum dimensions of the LCD, although the pixels are
// numbered from zero to (MAX-1).  Address may automatically
// be incremented after each transmission.
#define MAX_X                   84
#define MAX_Y                   48

#define DC                      (*((volatile unsigned long *)0x40004100))
#define DC_COMMAND              0
#define DC_DATA                 0x40
#define RESET                   (*((volatile unsigned long *)0x40004200))
#define RESET_LOW               0
#define RESET_HIGH              0x80
#define GPIO_PORTA_DIR_R        (*((volatile unsigned long *)0x40004400))
#define GPIO_PORTA_AFSEL_R      (*((volatile unsigned long *)0x40004420))
#define GPIO_PORTA_DEN_R        (*((volatile unsigned long *)0x4000451C))
#define GPIO_PORTA_AMSEL_R      (*((volatile unsigned long *)0x40004528))
#define GPIO_PORTA_PCTL_R       (*((volatile unsigned long *)0x4000452C))
#define SSI0_CR0_R              (*((volatile unsigned long *)0x40008000))
#define SSI0_CR1_R              (*((volatile unsigned long *)0x40008004))
#define SSI0_DR_R               (*((volatile unsigned long *)0x40008008))
#define SSI0_SR_R               (*((volatile unsigned long *)0x4000800C))
#define SSI0_CPSR_R             (*((volatile unsigned long *)0x40008010))
#define SSI0_CC_R               (*((volatile unsigned long *)0x40008FC8))
#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
                                            // Enable
#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
#define SSI_CC_CS_M             0x0000000F  // SSI Baud Clock Source
#define SSI_CC_CS_SYSPLL        0x00000000  // Either the system clock (if the
                                            // PLL bypass is in effect) or the
                                            // PLL output (default)
#define SYSCTL_RCGC1_R          (*((volatile unsigned long *)0x400FE104))
#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
#define SYSCTL_RCGC2_GPIOA      0x00000001  // port A Clock Gating Control


// This table contains the hex values that represent pixels
// for a font that is 5 pixels wide and 8 pixels high
static const char ASCII[][5] = {
  {0x00, 0x00, 0x00, 0x00, 0x00} // 20
  ,{0x00, 0x00, 0x5f, 0x00, 0x00} // 21 !
  ,{0x00, 0x07, 0x00, 0x07, 0x00} // 22 "
  ,{0x14, 0x7f, 0x14, 0x7f, 0x14} // 23 #
  ,{0x24, 0x2a, 0x7f, 0x2a, 0x12} // 24 $
  ,{0x23, 0x13, 0x08, 0x64, 0x62} // 25 %
  ,{0x36, 0x49, 0x55, 0x22, 0x50} // 26 &
  ,{0x00, 0x05, 0x03, 0x00, 0x00} // 27 '
  ,{0x00, 0x1c, 0x22, 0x41, 0x00} // 28 (
  ,{0x00, 0x41, 0x22, 0x1c, 0x00} // 29 )
  ,{0x14, 0x08, 0x3e, 0x08, 0x14} // 2a *
  ,{0x08, 0x08, 0x3e, 0x08, 0x08} // 2b +
  ,{0x00, 0x50, 0x30, 0x00, 0x00} // 2c ,
  ,{0x08, 0x08, 0x08, 0x08, 0x08} // 2d -
  ,{0x00, 0x60, 0x60, 0x00, 0x00} // 2e .
  ,{0x20, 0x10, 0x08, 0x04, 0x02} // 2f /
  ,{0x3e, 0x51, 0x49, 0x45, 0x3e} // 30 0
  ,{0x00, 0x42, 0x7f, 0x40, 0x00} // 31 1
  ,{0x42, 0x61, 0x51, 0x49, 0x46} // 32 2
  ,{0x21, 0x41, 0x45, 0x4b, 0x31} // 33 3
  ,{0x18, 0x14, 0x12, 0x7f, 0x10} // 34 4
  ,{0x27, 0x45, 0x45, 0x45, 0x39} // 35 5
  ,{0x3c, 0x4a, 0x49, 0x49, 0x30} // 36 6
  ,{0x01, 0x71, 0x09, 0x05, 0x03} // 37 7
  ,{0x36, 0x49, 0x49, 0x49, 0x36} // 38 8
  ,{0x06, 0x49, 0x49, 0x29, 0x1e} // 39 9
  ,{0x00, 0x36, 0x36, 0x00, 0x00} // 3a :
  ,{0x00, 0x56, 0x36, 0x00, 0x00} // 3b ;
  ,{0x08, 0x14, 0x22, 0x41, 0x00} // 3c <
  ,{0x14, 0x14, 0x14, 0x14, 0x14} // 3d =
  ,{0x00, 0x41, 0x22, 0x14, 0x08} // 3e >
  ,{0x02, 0x01, 0x51, 0x09, 0x06} // 3f ?
  ,{0x32, 0x49, 0x79, 0x41, 0x3e} // 40 @
  ,{0x7e, 0x11, 0x11, 0x11, 0x7e} // 41 A
  ,{0x7f, 0x49, 0x49, 0x49, 0x36} // 42 B
  ,{0x3e, 0x41, 0x41, 0x41, 0x22} // 43 C
  ,{0x7f, 0x41, 0x41, 0x22, 0x1c} // 44 D
  ,{0x7f, 0x49, 0x49, 0x49, 0x41} // 45 E
  ,{0x7f, 0x09, 0x09, 0x09, 0x01} // 46 F
  ,{0x3e, 0x41, 0x49, 0x49, 0x7a} // 47 G
  ,{0x7f, 0x08, 0x08, 0x08, 0x7f} // 48 H
  ,{0x00, 0x41, 0x7f, 0x41, 0x00} // 49 I
  ,{0x20, 0x40, 0x41, 0x3f, 0x01} // 4a J
  ,{0x7f, 0x08, 0x14, 0x22, 0x41} // 4b K
  ,{0x7f, 0x40, 0x40, 0x40, 0x40} // 4c L
  ,{0x7f, 0x02, 0x0c, 0x02, 0x7f} // 4d M
  ,{0x7f, 0x04, 0x08, 0x10, 0x7f} // 4e N
  ,{0x3e, 0x41, 0x41, 0x41, 0x3e} // 4f O
  ,{0x7f, 0x09, 0x09, 0x09, 0x06} // 50 P
  ,{0x3e, 0x41, 0x51, 0x21, 0x5e} // 51 Q
  ,{0x7f, 0x09, 0x19, 0x29, 0x46} // 52 R
  ,{0x46, 0x49, 0x49, 0x49, 0x31} // 53 S
  ,{0x01, 0x01, 0x7f, 0x01, 0x01} // 54 T
  ,{0x3f, 0x40, 0x40, 0x40, 0x3f} // 55 U
  ,{0x1f, 0x20, 0x40, 0x20, 0x1f} // 56 V
  ,{0x3f, 0x40, 0x38, 0x40, 0x3f} // 57 W
  ,{0x63, 0x14, 0x08, 0x14, 0x63} // 58 X
  ,{0x07, 0x08, 0x70, 0x08, 0x07} // 59 Y
  ,{0x61, 0x51, 0x49, 0x45, 0x43} // 5a Z
  ,{0x00, 0x7f, 0x41, 0x41, 0x00} // 5b [
  ,{0x02, 0x04, 0x08, 0x10, 0x20} // 5c '\'
  ,{0x00, 0x41, 0x41, 0x7f, 0x00} // 5d ]
  ,{0x04, 0x02, 0x01, 0x02, 0x04} // 5e ^
  ,{0x40, 0x40, 0x40, 0x40, 0x40} // 5f _
  ,{0x00, 0x01, 0x02, 0x04, 0x00} // 60 `
  ,{0x20, 0x54, 0x54, 0x54, 0x78} // 61 a
  ,{0x7f, 0x48, 0x44, 0x44, 0x38} // 62 b
  ,{0x38, 0x44, 0x44, 0x44, 0x20} // 63 c
  ,{0x38, 0x44, 0x44, 0x48, 0x7f} // 64 d
  ,{0x38, 0x54, 0x54, 0x54, 0x18} // 65 e
  ,{0x08, 0x7e, 0x09, 0x01, 0x02} // 66 f
  ,{0x0c, 0x52, 0x52, 0x52, 0x3e} // 67 g
  ,{0x7f, 0x08, 0x04, 0x04, 0x78} // 68 h
  ,{0x00, 0x44, 0x7d, 0x40, 0x00} // 69 i
  ,{0x20, 0x40, 0x44, 0x3d, 0x00} // 6a j
  ,{0x7f, 0x10, 0x28, 0x44, 0x00} // 6b k
  ,{0x00, 0x41, 0x7f, 0x40, 0x00} // 6c l
  ,{0x7c, 0x04, 0x18, 0x04, 0x78} // 6d m
  ,{0x7c, 0x08, 0x04, 0x04, 0x78} // 6e n
  ,{0x38, 0x44, 0x44, 0x44, 0x38} // 6f o
  ,{0x7c, 0x14, 0x14, 0x14, 0x08} // 70 p
  ,{0x08, 0x14, 0x14, 0x18, 0x7c} // 71 q
  ,{0x7c, 0x08, 0x04, 0x04, 0x08} // 72 r
  ,{0x48, 0x54, 0x54, 0x54, 0x20} // 73 s
  ,{0x04, 0x3f, 0x44, 0x40, 0x20} // 74 t
  ,{0x3c, 0x40, 0x40, 0x20, 0x7c} // 75 u
  ,{0x1c, 0x20, 0x40, 0x20, 0x1c} // 76 v
  ,{0x3c, 0x40, 0x30, 0x40, 0x3c} // 77 w
  ,{0x44, 0x28, 0x10, 0x28, 0x44} // 78 x
  ,{0x0c, 0x50, 0x50, 0x50, 0x3c} // 79 y
  ,{0x44, 0x64, 0x54, 0x4c, 0x44} // 7a z
  ,{0x00, 0x08, 0x36, 0x41, 0x00} // 7b {
  ,{0x00, 0x00, 0x7f, 0x00, 0x00} // 7c |
  ,{0x00, 0x41, 0x36, 0x08, 0x00} // 7d }
  ,{0x10, 0x08, 0x08, 0x10, 0x08} // 7e ~
//  ,{0x78, 0x46, 0x41, 0x46, 0x78} // 7f DEL
  ,{0x1f, 0x24, 0x7c, 0x24, 0x1f} // 7f UT sign
};

enum typeOfWrite{
  COMMAND,                              // the transmission is an LCD command
  DATA                                  // the transmission is data
};
// The Data/Command pin must be valid when the eighth bit is
// sent.  The SSI module has hardware input and output FIFOs
// that are 8 locations deep.  Based on the observation that
// the LCD interface tends to send a few commands and then a
// lot of data, the FIFOs are not used when writing
// commands, and they are used when writing data.  This
// ensures that the Data/Command pin status matches the byte
// that is actually being transmitted.
// The write command operation waits until all data has been
// sent, configures the Data/Command pin for commands, sends
// the command, and then waits for the transmission to
// finish.
// The write data operation waits until there is room in the
// transmit FIFO, configures the Data/Command pin for data,
// and then adds the data to the transmit FIFO.

// This is a helper function that sends an 8-bit message to the LCD.
// inputs: type     COMMAND or DATA
//         message  8-bit code to transmit
// outputs: none
// assumes: SSI0 and port A have already been initialized and enabled
void static lcdwrite(enum typeOfWrite type, char message){
  if(type == COMMAND){
                                        // wait until SSI0 not busy/transmit FIFO empty
    while((SSI0_SR_R&SSI_SR_BSY)==SSI_SR_BSY){};
    DC = DC_COMMAND;
    SSI0_DR_R = message;                // command out
                                        // wait until SSI0 not busy/transmit FIFO empty
    while((SSI0_SR_R&SSI_SR_BSY)==SSI_SR_BSY){};
  } else{
    while((SSI0_SR_R&SSI_SR_TNF)==0){}; // wait until transmit FIFO not full
    DC = DC_DATA;
    SSI0_DR_R = message;                // data out
  }
}

//********Nokia5110_Init*****************
// Initialize Nokia 5110 48x84 LCD by sending the proper
// commands to the PCD8544 driver.  One new feature of the
// LM4F120 is that its SSIs can get their baud clock from
// either the system clock or from the 16 MHz precision
// internal oscillator.
// inputs: none
// outputs: none
// assumes: system clock rate of 80 MHz
void Nokia5110_Init(void){
  volatile unsigned long delay;
  SYSCTL_RCGC1_R |= SYSCTL_RCGC1_SSI0;  // activate SSI0
  SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA; // activate port A
  delay = SYSCTL_RCGC2_R;               // allow time to finish activating
  GPIO_PORTA_DIR_R |= 0xC0;             // make PA6,7 out
  GPIO_PORTA_AFSEL_R |= 0x2C;           // enable alt funct on PA2,3,5
  GPIO_PORTA_AFSEL_R &= ~0xC0;          // disable alt funct on PA6,7
  GPIO_PORTA_DEN_R |= 0xEC;             // enable digital I/O on PA2,3,5,6,7
                                        // configure PA2,3,5 as SSI
  GPIO_PORTA_PCTL_R = (GPIO_PORTA_PCTL_R&0xFF0F00FF)+0x00202200;
                                        // configure PA6,7 as GPIO
  GPIO_PORTA_PCTL_R = (GPIO_PORTA_PCTL_R&0x00FFFFFF)+0x00000000;
  GPIO_PORTA_AMSEL_R &= ~0xEC;          // disable analog functionality on PA2,3,5,6,7
  SSI0_CR1_R &= ~SSI_CR1_SSE;           // disable SSI
  SSI0_CR1_R &= ~SSI_CR1_MS;            // master mode
                                        // configure for system clock/PLL baud clock source
  SSI0_CC_R = (SSI0_CC_R&~SSI_CC_CS_M)+SSI_CC_CS_SYSPLL;
                                        // clock divider for 3.33 MHz SSIClk (80 MHz PLL/24)
                                        // SysClk/(CPSDVSR*(1+SCR))
                                        // 80/(24*(1+0)) = 3.33 MHz (slower than 4 MHz)
  SSI0_CPSR_R = (SSI0_CPSR_R&~SSI_CPSR_CPSDVSR_M)+24; // must be even number
  SSI0_CR0_R &= ~(SSI_CR0_SCR_M |       // SCR = 0 (3.33 Mbps data rate)
                  SSI_CR0_SPH |         // SPH = 0
                  SSI_CR0_SPO);         // SPO = 0
                                        // FRF = Freescale format
  SSI0_CR0_R = (SSI0_CR0_R&~SSI_CR0_FRF_M)+SSI_CR0_FRF_MOTO;
                                        // DSS = 8-bit data
  SSI0_CR0_R = (SSI0_CR0_R&~SSI_CR0_DSS_M)+SSI_CR0_DSS_8;
  SSI0_CR1_R |= SSI_CR1_SSE;            // enable SSI

  RESET = RESET_LOW;                    // reset the LCD to a known state
  for(delay=0; delay<10; delay=delay+1);// delay minimum 100 ns
  RESET = RESET_HIGH;                   // negative logic

  lcdwrite(COMMAND, 0x21);              // chip active; horizontal addressing mode (V = 0); use extended instruction set (H = 1)
                                        // set LCD Vop (contrast), which may require some tweaking:
  lcdwrite(COMMAND, CONTRAST);          // try 0xB1 (for 3.3V red SparkFun), 0xB8 (for 3.3V blue SparkFun), 0xBF if your display is too dark, or 0x80 to 0xFF if experimenting
  lcdwrite(COMMAND, 0x04);              // set temp coefficient
  lcdwrite(COMMAND, 0x14);              // LCD bias mode 1:48: try 0x13 or 0x14

  lcdwrite(COMMAND, 0x20);              // we must send 0x20 before modifying the display control mode
  lcdwrite(COMMAND, 0x0C);              // set display control to normal mode: 0x0D for inverse
}

//********Nokia5110_OutChar*****************
// Print a character to the Nokia 5110 48x84 LCD.  The
// character will be printed at the current cursor position,
// the cursor will automatically be updated, and it will
// wrap to the next row or back to the top if necessary.
// One blank column of pixels will be printed on either side
// of the character for readability.  Since characters are 8
// pixels tall and 5 pixels wide, 12 characters fit per row,
// and there are six rows.
// inputs: data  character to print
// outputs: none
// assumes: LCD is in default horizontal addressing mode (V = 0)
void Nokia5110_OutChar(unsigned char data){
  int i;
  lcdwrite(DATA, 0x00);                 // blank vertical line padding
  for(i=0; i<5; i=i+1){
    lcdwrite(DATA, ASCII[data - 0x20][i]);
  }
  lcdwrite(DATA, 0x00);                 // blank vertical line padding
}

//********Nokia5110_OutString*****************
// Print a string of characters to the Nokia 5110 48x84 LCD.
// The string will automatically wrap, so padding spaces may
// be needed to make the output look optimal.
// inputs: ptr  pointer to NULL-terminated ASCII string
// outputs: none
// assumes: LCD is in default horizontal addressing mode (V = 0)
void Nokia5110_OutString(unsigned char *ptr){
  while(*ptr){
    Nokia5110_OutChar((unsigned char)*ptr);
    ptr = ptr + 1;
  }
}

//********Nokia5110_OutUDec*****************
// Output a 16-bit number in unsigned decimal format with a
// fixed size of five right-justified digits of output.
// Inputs: n  16-bit unsigned number
// Outputs: none
// assumes: LCD is in default horizontal addressing mode (V = 0)
void Nokia5110_OutUDec(unsigned short n){
  if(n < 10){
    Nokia5110_OutString("    ");
    Nokia5110_OutChar(n+'0'); /* n is between 0 and 9 */
  } else if(n<100){
    Nokia5110_OutString("   ");
    Nokia5110_OutChar(n/10+'0'); /* tens digit */
    Nokia5110_OutChar(n%10+'0'); /* ones digit */
  } else if(n<1000){
    Nokia5110_OutString("  ");
    Nokia5110_OutChar(n/100+'0'); /* hundreds digit */
    n = n%100;
    Nokia5110_OutChar(n/10+'0'); /* tens digit */
    Nokia5110_OutChar(n%10+'0'); /* ones digit */
  }
  else if(n<10000){
    Nokia5110_OutChar(' ');
    Nokia5110_OutChar(n/1000+'0'); /* thousands digit */
    n = n%1000;
    Nokia5110_OutChar(n/100+'0'); /* hundreds digit */
    n = n%100;
    Nokia5110_OutChar(n/10+'0'); /* tens digit */
    Nokia5110_OutChar(n%10+'0'); /* ones digit */
  }
  else {
    Nokia5110_OutChar(n/10000+'0'); /* ten-thousands digit */
    n = n%10000;
    Nokia5110_OutChar(n/1000+'0'); /* thousands digit */
    n = n%1000;
    Nokia5110_OutChar(n/100+'0'); /* hundreds digit */
    n = n%100;
    Nokia5110_OutChar(n/10+'0'); /* tens digit */
    Nokia5110_OutChar(n%10+'0'); /* ones digit */
  }
}

//********Nokia5110_SetCursor*****************
// Move the cursor to the desired X- and Y-position.  The
// next character will be printed here.  X=0 is the leftmost
// column.  Y=0 is the top row.
// inputs: newX  new X-position of the cursor (0<=newX<=11)
//         newY  new Y-position of the cursor (0<=newY<=5)
// outputs: none
void Nokia5110_SetCursor(unsigned char newX, unsigned char newY){
  if((newX > 11) || (newY > 5)){        // bad input
    return;                             // do nothing
  }
  // multiply newX by 7 because each character is 7 columns wide
  lcdwrite(COMMAND, 0x80|(newX*7));     // setting bit 7 updates X-position
  lcdwrite(COMMAND, 0x40|newY);         // setting bit 6 updates Y-position
}

//********Nokia5110_Clear*****************
// Clear the LCD by writing zeros to the entire screen and
// reset the cursor to (0,0) (top left corner of screen).
// inputs: none
// outputs: none
void Nokia5110_Clear(void){
  int i;
  for(i=0; i<(MAX_X*MAX_Y/8); i=i+1){
    lcdwrite(DATA, 0x00);
  }
  Nokia5110_SetCursor(0, 0);
}

//********Nokia5110_DrawFullImage*****************
// Fill the whole screen by drawing a 48x84 bitmap image.
// inputs: ptr  pointer to 504 byte bitmap
// outputs: none
// assumes: LCD is in default horizontal addressing mode (V = 0)
void Nokia5110_DrawFullImage(const char *ptr){
  int i;
  Nokia5110_SetCursor(0, 0);
  for(i=0; i<(MAX_X*MAX_Y/8); i=i+1){
    lcdwrite(DATA, ptr[i]);
  }
}