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DSP Access to L4_PER/GPIO

michael clark
Intellectual 520 points


I'm trying to access GPIO modules 6 & 8 from the DSP subsystem on the OMAP54xEVM. I keep receiving a "l3 custom error" from the kernel when reading the base register ( GPIO_REVISION ). The DSP AMMU and MMU are configured properly, so I'm confused if this is a connectivity or permissions (firewall) issue. I also noticed that the DSP seems to have R/W permissions to GPIO modules 3,5,7 because no kernel errors are reported, and a valid (non-zero) revision ID is reported (0x50602001).

I went through most of the L4_PER AP (Address Protection) registers, and it looks like there are no restrictions (default settings). From TRM Figure 14-2 Connectivity Matrix, it says that there is only a functional path between the DSP and L4_PER_P3. What is L4_PER_P3?

Is there any chance the DSP can access GPIO modules 6 or 8? I'm planning to use the I2C, McBSP3, CPI and GPMC interfaces, so there aren't many available GPIO pins that support interrupts (GPIO 2-6).

Thanks!

  • 0
    TI__Guru**** 161600 points

    Hi Michael,

    l3 custom errors do not indicate address hole (connectivity issue) or permission (firewall) errors, it simply means that the GPIO module itself sends an error signal (SResp= ERROR)  to L3 NoC.  In these cases the issue is not in the L3 NoC, but in the target itself (in your case GPIO).

    I suggest checking GPIO configuration? As a start can you verify that GPIO 6 & 8  clocks are properly enabled in PRCM?

    michael clark said:
    What is L4_PER_P3?

    L4_PER has four ports (P0/P1/P2/P3) through which it connects to L3 NOC, L4_PER_P3 indicates the 4th of these ports. See Figure 14-9. L4 Interconnect Overview.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Intellectual 520 points

    Yordan, thanks for clarifying the "l3 custom error" definition. The clocks were in fact disabled, and GPIO modules 6 & 8 are now working as expected. Thanks for the help!