One of our customer finalized to use TI LM98620 ADC for the CCD frontend.
The datasheet refers to development board schematics & layout (page 59 & 64) for guidelines.
Can anyone please share the schematics for LM98620 evaluation board.
1) Here is the LM98620 bench board documentation (Board / Gerber files, schematic, floor plan, BOM). Note that the LM98620 uses the LM98618 bench testing board (Note: The board is not available for sale or demo to customer).
• LM98620 Bench Board 012770_r2 Hooman_2_25_16 link (click here)
2) Here is the SensorEval installation file, and instructions, including an LM98620 register file example (*.dat), for your reference:
• SensorEval 1.1.5 AFE link (click here)
Please let me know if you have any questions.
In reply to Hooman Hashemi:
In reply to syed hamad:
What is the timing for generating CLPIN & BLKCLP. Is it during the light shield output (blanking period) from sensor.
I have attached the timing chart of the CCD sensor I am using.
In reply to Prasanna Ganapathi:
Yes, the CLPIN and BLKCLP inputs should be asserted during the Light shield output pixels.
Please refer to Figure 21 and Figure 24 and related text descriptions in the LM98620 datasheet.
In reply to Jim Brinkhurst84999:
For SH1a mode you can leave the DLL sample position settings at defaults.
You do not need to drive the SHD/HOLD or SHP/SAMPLE inputs. The sample and hold timing is driven from AFEPHASE internal timing signal.
I recommend you use a Pixel Rate input clock. Then the internal AFEPHASE timing is determined by the input clock and no other external timing signal is required.
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