LMG5200 Simulation Dead Time V.S. Power Loss

Leonid

The minimum recommended dead times of the LMG5200 are mainly due to the driver we have inside. It is a slightly improved version of our LM5113 with approximately 30ns of latency and skew matching of approximately 2ns between the high side and low side drive inputs and should support minimum dead times of 6ns or so between the HI input and LI input.  Please reply with the schematic of the the circuit connected to the SW outputs so we can see more details.

It is unclear from the attached schematic if you have independent logical inputs to pin 1 of U6 and U7 that should be 180deg out of phase. . 

Here is an updated picture showing that the inputs to U6 and U7 are 180 out of phase. Also you can see the output filter and load.

Grant,

I have attached the full file to the post. I had to change the modulation as I cannot give you my actual modulator but you can still clearly tell that the power changes drastically by changing the value of capacitors C12 and C13. With 28pF the power dissipation is about 3W but with 10pF the power dissipation is close to 30W.

Regards;

Leo

0537.GaN_Full_Bridge_PWM_ONLY.TSC

Leo

I simulated your file (note that it is not recommended to tie the bootstrap cap to the SW node, see page 7 of the LMG5200 EVM User guide 

snvu461.pdf). With the way you have the input excitation, it looks like a 5KHz 100W sine generator, with the output cycling between +/-40V into 8 ohms.

Maintaining minimum dead times during the peaks and valleys of designs like this can be tricky. We often see blanking being added to turn on side completely on or off to minimize the possibility of shoot through. There are even more exotic modulation approaches for Class-D audio applications that gaurentee minimum dead times are met.  Parts like the LMG5200 should make for some really low THD class-D audio designs due to the short rise and fall times of the SW nodes.

In your design I see that there are dead times less than our recommended 8ns or so around the 50us and 250us (and every 200us cycle there after) mark. See the tina screen shot below showing less than 5ns between U1_HI going low and U2_HI going high. This is also where the power at the load is a maximum of about 200W.  Note how the voltage on U1 SW node gets a ramp to its leading edge, indicating that increased switching losses are occurring or, maybe even internal shoot through.

Grant,

In the design I tied HS to the switch node because that is what your Tina reference design is doing here http://www.ti.com/lit/tsc/snom478. If you remove that connection the simulation does not seem to run well.

Also I cannot figure out why the logic gates are only going to 3.4V, is this some internal Tina thing?

Can you suggest a part to use in Tina that has a Schmitt triggered input?

I am also not exactly understanding what you are telling me in regard to the dead time in my circuit which I have used for years to simulated dead time a 10pF capacitor shall provide 10nS of dead time. I cannot figure out why in Tina this is not the case... In pspice and ltspice I get 10ns no matter where in the sine wave we are. Is this something to do with the way Tina implements SN74 series gates?

Thanks;

Leo

Leo

I tried the downloadable LMG5200 tina simulation *.tsc file with HS not tied to the SW node and dont see any sim issues. I will request that we change the file to agree with our LM5113 Tina file where the HS and HB nodes are not tied to anything but the cap. Note that the LM5113 TINA file uses about 50ns of dead time.

It may be a TINA thing on the output drive of the AND gate and have elevated it to our TINA support group. If you look at the RC Ramp voltage on the input of the gate around the 50us mark you will see that the output of the gate changes about 4ns after the other input, probably just the prop delay of the gate.

There are 200K pull downs on the input of the LMG5200. At 5V the current required to drive it above 4V is only 20uA, which the gate should easily drive.

Grand if you look at the file that I posted earlier, it will not run with the HS node of the LMG5200 not tied to the respective switch node. Maybe there is some other issue going on as well. I tried to increase the dead time and still does no work.

/cfs-file/__key/communityserver-discussions-components-files/196/8400.GaN_5F00_Full_5F00_Bridge_5F00_PWM_5F00_ONLY.TSC

It seems to be working properly now. Thanks for all your help

Hi Leo, Grant,

I was browsing around on e2e and came across your post. GaN (and SPICE) being an interest of mine I decided to play with your simulation a bit. I modified the load to be a true dynamic speaker impedance, tweaked the analysis parameters and replace the NAND gate with a behavioral model. TINA calculates an efficiency of 75.38/77.39 = 97.4%, but this does not include losses in the recovery filter of the amplifier. Simulation runs faster.

GaN_Full_Bridge_PWM_ONLY-final_jcr.TSC

See if the attachment works better for you.

Best regards,

John Rice