UCC28070 PWM Outputs GDx not generating

What is the value of VSS ?
The ic is only enabled once VSS rises above 0.75V nominal, 0.85V max

What is the output voltage of the pfc with 200Vac input ?

The gate drive outputs are disabled until VSENSE = 0.75V nominal and 0.85V max
What voltage do you measure at VSENSE?

The soft start is disabled until VAO is less than 0.75V. This is a zero power demand level.
After this condition is met, then the pfc should start up and you will get gate drive pulses.

VAO is the output of the voltage error amplifier and should not remain at the 0V level.

Hello,

Thank you very much for your quick response. Based on your reply, we have carried our following measurement at 200V AC input.

Input	200VAC
DC Bus	288V
VAO	0V
VSS	1.05V
VSENSE	2.4V
VINAC (RMS)	1.4V
VCC	12V
VREF	6V
Voltage at CAOA	0V
Voltage at CAOB	0V
Voltage at PKLMT	3.7V
GDA	No PWM
GDB	No PWM

Please let us know how to proceed further.

Thanks & Regards,

Dhoresh.

VSS is too low. For a normal start it should rise to 3V. The reason you are not getting gate drive signals is that the soft start voltage is below VSENSE voltage and therefore VAO is zero.
You should find out what is pulling VSS low and preventing it from rising above 2.4V

Hello,

Thank you for quick and valuable response.

In reference schematic slur217 (PMP4259_POWER_REVB.sch, attached) we found that the MOSFET (2N7002W) Q5 used to pull down SS Pin having VGTH (threshold voltage) minimum 1V. That means this MOSFET will be continuously switched ON once U2 (TL431AIDBZ) is ON. Due to this SS pin was low below VSENSE. We could not find Q5 part number in the reference BOM slur096 (PMP4259_POWER_REVB_bom.xls). Can you tell what is the exact part number used on the evaluation board as feel part number shown in schematic will not work.

Here we have tried with Si2328DS this MOSFET in place of 2N7002W (at Q5) and tried to power ON with variac slowly increasing the voltage, after 100VAC fuse is blown. Then we found that PFC MOSFETS Q1to Q4 were damaged. By this we believe PWM GDx would have started.

As in reference design slur294 (PMP4259_Controller_REVB.sch), the pull down resistor at DMAX (pin no 20) is 180k (R32)and RT (pin no 19) is 200k (R31). As per our calculations PWM frequency will be 37.5KHz and Duty cycle will be 95%. Is 95% duty cycle is acceptable or not?

Can you suggest what might be the reason for failure of the MOSFETs. Also suggest few tentative part numbers  to be used at Q5.

Thanks,

Dhoresh.

PFC Related.zip

Hello,

We are waiting for your reply. Please reply as soon as possible.

Did you build the PMP4259 reference design ?

Or are we still talking about the pfc circuit attached in the initial question?

Have you found out what is pulling the SS pin low?

The PMP4259 reference design does not have Q5  in the BOM and it is not fitted in the assembly.

The under voltage protection is disabled, most likely because it did not work and the pcb assembly was never updated to enable under voltage protection.

Yes we are talking about PFC Circuit attached in initial question, but that was almost a copy of PM4259 design. Yes we find that SS pin is getting pull down by Q5.

If we remove Q5 and switch ON the board both Fuse and PFC MOSFETs are getting damaged. So what are the other changes to be done which are present in schematic and not present in BOM or on actual PCB. As it was confusing for us that something is shown in schematic and BOM is something different.

Thanks,

Dhoresh.

Hello John Griffin,
One more observation from the BOM for RT1 and RT2, in description it shows "Thermistor, NTC, 10 ohms, 8-A", but part number is B57464S0509M000, which is a 5 Ohms part. So which one to be used as per design 5Ohm or 10 Ohm. Actually we have one doubt whether this design can be trusted or not. Please make it clear as we are seeing many missings between schematic and BOM and again in BOM itself differences. Please clarify as soon as possible.

Hello,

We are waiting for your response. Please reply as soon as possible.

Thanks,

Dhoresh.

Hello,
From long time there was no reply for this post. I don't know why no one from TI is responding to this. Now I feel that there is a problem in this reference design and I also feel that this reference design never worked with TI also. At-least let us know if something is seriously wrong about this design, if so we want to go for some other design. I never expected this kind of support from TI. Please conclude as soon as possible whether we can go with this design or do you suggest any alternate design.
Thanks,
Dhoresh.

Hello,

This issue has been closed.
We need a small cap post rectifier stage. Additionally, proper care needs to be taken during layout, other wise excessive ringing would be observed at switch node, which will limit the operation of the design at higher input voltage, which will cause MOSFETs to fail.

Thanks and Regards,
Mahendra Patel