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tps40054 INITAL DEBUG. Unit appears to be stuck in fault condition with no load applied

Todd Hughes
Prodigy 100 points
  • 0
    TI__Genius 17240 points

    Hi Tod,

    What the fault mode the IC gets into? Can you check the SS pin to see whether it stays low or stays in the soft-start cycles?

    If SS stays low, the IC may get into UVLO, examine your UVLO setup circuit.

    If it stays in the soft-start cycles, the IC may run into overcurrent protection. It is possible when tstart is too short. Try to increase the Css to extend tstart, so that the output charge current (VoutCout/tstart) is less than the current limit minus start-up current demanded by the load.

    Regards,

    Na

  • 0 in reply to Na Kong
    Prodigy 100 points

    Na-

     

    The supply looks like it is staying in soft start. My L = 10uH and Co = 150uF. I increased the Css to 0.1uF and reduced the R_lim = 10K. With these values I can now see the voltage ramp at the inductor input for about 60 msec and the waits a bit and repeats. I can also the voltage beginning to rise on the output cap. What do I need to look at now???

     

    Thx-

    Todd

  • 0 in reply to Todd Hughes
    TI__Genius 17240 points

    Hi Todd,

    What is your input voltage, output voltage, switching frequency and what are the MOSFETs used? What do you mean by "inductor input"?

    Based on your description, I guess the converter tries to restart  but always trips the current limit. If the soft-start time is long enough, another possibility is the dv/dt induced turn-on described on page 20 of the datasheet. You can check switching node voltage and HDRV. During on-time (HDRV is high), Vsw should be close to the input voltage. If bottom FET is turned on by the dv/dt, Vsw will be pulled down. If this happens, you should also see the supply current surges.

    Regards,

    Na 

  • 0 in reply to Na Kong
    Prodigy 100 points

    Na-

     

    Sorry for the delayed response but i've been away from my computer.

    Input voltage: 18 - 30 VDC

    Ouput voltage: 11 VDC

    Fsw : 330KHz

    The node I was referring too is the connection of the FETs to the inductor.

    FETs : Si7460DP

    I have not had a chance to go to the lab and make the measurement  you requested yet.

     

    Thanks-

    Todd

  • 0 in reply to Todd Hughes
    Prodigy 100 points

    Na-

     

    It does appear that the bottom FET is turning on due to the dv/dt. The appnote mentions adding capacitance to the low FET gate drive signal.

    What is the max before I risk damaging the output?

    Also is a better solution to use a FET that does not have a logic level gate input?

     Finally can I test without the bottom FET in the circuit and temporarily use a Schottky diode in its place?

     If I do this do I need to terminate the gate signal with a 1K resistor to GND?

     

    Thanks for your help.

     

    Todd

  • 0 in reply to Todd Hughes
    TI__Genius 17240 points

    Todd,

    There are several possible solutions for this issue.

    (1) Slow down dV/dt on the switching node by adding boot resistor or driving resistor. The boot resistor is in series with the boot capacitor between BOOST and SW. Driving resistor is the one between HDRV and gate of the top FET. Boot resistor is considered the most efficient solution since it just affect the rising speed, while driving resistor affects both rising and falling speed, therefore leads to more switching loss. 5 ohm boot resistor is a good start point, If it is not big enough, you may try upto 10 ohm.

    (2) Add external capacitor in parallel with the Cgs of the bottom FET. The drawback is more driver loss and conduction loss because the body-diode conduction time will be longer. You can try with 10nF. The lead of the capacitor to the FET should be as short as possible. Replacing the bottom FET with one that has higher threshold and Cgs/Cgd ratio is better than this remedy.

    (3)  If you want to temporarily use a shcottky diode, you can terminate the LDRV with a 100pF capacitor to GND or leave it floating. 100pF capacitor is better to reduce the noise.

    (4) If you will work on another layout, the trace parasitic resistance and inductance  from LDRV pin to the gate of the bottom FET should be as small as possible.

    To sum up, I will suggest to try (1) first. If it cannot solve the problem, then maybe in conjunction with (2). You have to garantee the solution is effective under the worst case of VIN, or maximum VIN.

    Regards,

    Na

  • 0 in reply to Na Kong
    Prodigy 100 points

    Na-

    I have tried several of your recommendations and still experiencing some issues.

    1 - I have an 8.2 Ohm resistor already in the design.

    2 - I haven't switched FETs yet but this is a viable option. I have a external cap on the gate but in reviewing the layout it is not in an optimal location. I may need to attached it directly at the FET.

    3 - I replaced bottom FET with a diode. I had additional trouble. Unit still would not output voltage. And the high side FET short gate to source. It took me a long time to find this fault. The source must have gotten higher than the gate and damaged the FET.

    4- Before I do another layout I need to get this version outputting voltage if at all possible. I know there are tweaks to the layout that need to be made. For instance, the Rlim resistor does not have a proper Kelvin conection to the High side FET drain.

    Anyway to facilitate the debug should/can I change the Rlim and Cap to suppress the current limit and disable the feedforward so that I am voltage mode feedback only? Are there other things I could eliminate to allow me to get the unit to run steady state at a limited input range and limited load.

     

    Thanks-

    Todd

     

  • 0 in reply to Todd Hughes
    TI__Genius 17240 points

    Hi Todd,

    One thing I am not clear from you description is that the high side FET short gate to source happened before you replaced the bottom FET with diode or after. If it happened before, I think it's due to the dv/dt turn-on. The switching node may have high speed and high amplitude osccilation which cause the short from gate to source of top FET because Vgs is either too high or too negative. I feel it is less likely to have top FET gate and source shorted after you replaced the FET with diode.

    If you have replaced the bottom FET with a diode, then you should not have the dv/dt turn on. So no needs to change Rlim to suppress the current limit and it actually doesn't help to suppress dv/dt. I also didn't see the advantage by disabling the feedforward, since you need to redesign the compensator.

    Regards,

    Na

     

  • 0 in reply to Na Kong
    Prodigy 100 points

    Na-

    I thing the FET is getting damaged on powerup. Tested a new unit and measured ~15 Ohms gate to source on high side FET.

    Can I put a small gate resistor in the circuit and also a 12 V zener gate to source to clamp the oscillation?

     

    Also I have seen the output of the PWM have a 2V gae drive signal on the high side and no gate drive signal on the low side. Is the PWM damaed or is this a logic protection mode of the chip?

     

    Thanks-

     

    Todd Hughes

  • 0 in reply to Todd Hughes
    TI__Genius 17240 points

    Hi Todd,

    First, I need to understand under what condition the top FET is broken: were you using a low-side FET or a diode?

    If the SW pin of the IC also has experienced a negative voltage spike with an amplitude and transient  time beyond the absolute maximum rating, the controller may be damaged.

    Regards,
    Na

  • 0 in reply to Na Kong
    Prodigy 100 points

    Na-

     

    I am using the FET for the low side switch.

    One thing I am seeing is the high side FET drive active but the low side drive inactive. What could cause this condition?

    Also i am in the process of making changes to the layout to address the current limit resistor placement and some other minor changes. Is there a way i could forward the layout to TI for review prior to PCB fabrication?

     

    Thanks for all your assistance-

    Todd Hughes

  • 0 in reply to Todd Hughes
    TI__Genius 17240 points

    Hi Todd,

    Have you solved the dv/dt problem? When you see high side drive active and low side drive inactive, is the part a good one or the one has experience the dv/dt?

    You can upload your design here. I can take a look.

    Regards,

    Na

     

  • 0 in reply to Na Kong
    Prodigy 100 points

    Na-

     

    The unit I am testing is a new unit. With the lo side FET not turning on, I do not know if I have solved the dv/dt issue.

     

    I do think that the gate drive signals can be improved through routing. Also I thought about including a spot for gate resistors on the PCB. I would populate them with zero Ohm initally and only use them if needed.

    Attached is the schematic and the current board layout. As you can tell, I need to improve the placement of C22 for my dv/dt issue. Also the location and routing of R3 needs to improve the current limit sense. The gate drive signals need to improve to reduce the inductance. Please look at the the layout and recommend any additional changes. Finally the PCB has a power and ground plane but I did not include them in the post since they do not provide any additional detail.

    Thanks-

     

    Todd1778.12041-6055-01 PCBA-1_bot.pdf7230.12041-6055-01 PCBA-1_top.pdf1072.12041-6055-01 PCBA-1_bot_slk.pdf7230.12041-6055-01 PCBA-1_top_slk.pdf8562.harris_dc_adapter_sch.pdf

  • 0 in reply to Todd Hughes
    TI__Genius 17240 points

    Hi Todd,

    I have reviewed the new design and here are some suggestions.

    (1) Since you have seen the dv/dt caused by high Qgd/Qgs ratio of SI7460DP, I will suggest you pick another FET. By looking for FETs with similar Vds, Id, Rdson, gate charge, I have found IRF7855PbF (similar Qgd/Qgs ratio, but higher Vgs,th) and FDS5672 (lower Qgd/Qgs ratio, higher Vgs,th).

    (2) It is suggested to add a 0 ohm resistor from HDRV pin to the gate of Q1 just in case.

    (3) For the layout, the path from input supply to the top FET and its return from bottom FET to E2/E6 are not good. Why not connecting the C12 "+" terminal and Gate of Q1 directly on top layer? Otherwise, all the current needs to rush into the only via close to C12 "+" terminal to the pwr layer, and then back to the top layer through another 3 vias. I will also suggest add more vias close to C12 "+". The same problem for the return path. Since you don't have direct path on top or bottom, the only path is the ground layer. All the current will rush into the gnd layer through two vias. I am wondering why the gnd layer not covering the area underneath Q2, since I think it will improve efficiency and thermal performance.

    (4) The RC snubber circuit (R19 + C24) is used to protect Q2 from large voltage spike and ringing. Therefore, it should be placed as close to Q2 as possible. The trace from gate of Q2 to R19 and from source of Q2 to C24 should be shortened. Current connection of R19 and C24 with respect to Q2 may not serve its purpose.

    Regards,

    Na

  • 0 in reply to Na Kong
    Prodigy 100 points

    Na-

     

    Thanks for the feedback. With regards to item #3, I had placed a 10uF cap (C14) directly under the FETs for high frequency switching currents. I can improve the connection to the bulk cap (C12) but I thought that the bulk of the current would be supplied by C16.  On #4,  I will improve my snubber connection but I do not think  that i can move it much closer. Finally I am concerned about my voltage feedback connection running along the edge of the PCB below Q2. Will I experience issues with noise pickup on this trace?

     

    Thanks-

    Todd

  • 0 in reply to Todd Hughes
    TI__Genius 17240 points

    Hi Todd,

    I am not saying C16 will supply the bulk current or not. By tracking the input power delivery path to Q1, the via close to C12 is the only way the input power can flow, which is the bottleneck. Although you have a large VIN plane, most of the area will not be used.

    The voltage feedback connection is not ideal, but I think it should be fine.

    You are also welcome to refer to our EVM layout.

    Regards,

    Na