I have noticed the PGood pin momentarily goes high upon device enable, despite Vin being above 5V. On a custom board approx 11.5uS after enabling the device at the UVLO pin, Pgood goes high for ~373nS before being held low again as the device comes into regulation. Once in regulation pgood remains high (as expected).
The data sheet mentions "During turnon, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊ 5 V. PGD then
switches low, remaining low as the VIN voltage increases. When the voltage at OUT increases to within 1.25 V of
the SENSE pin (VDS <1.25 V), PGD switches high. PGD switches low if the VDS of Q1 increases above 2.5 V."
This implies Pgood is held low until Vout is within regulation and does not suggest a momentary registering of high.
I can also duplicate the behavior on the eval board. Attached are screen shots.LM5069_Pgood_TI.pptx
