TMS320DM6467: VPIF CLK

We use the TMS320DM6467ZUTA for H.264 video decoder,the video data is put out by VPIF interface,We use an external clk input to VPIF's VP_CLKIN0 pin from a FPGA' s PIn in the board,the output video data is put on the negative edge of the VP_CLKOUT2 pin, The FPGA receive the output video data on the resedge of the VP_CLKOUT2 in the image proceesor board. for some design constraint,We must use the FPGA's inner clk with  a fixed phase from the VP_CLKIN0 to recevice the output video data for another pass ,We want to know the delay phase bettween VPIF's VP_CLKIN0 and VP_CLKOUT2 in the TMS320DM6467ZUTA ,please sure the delay phase from the input and output pin,because We can't find the data from the device datasheet. and We wonder if it's a fixed delays phase in your device?