AM3359: Parallel NOR over BeagelBone black

Lior Yaron Benjamin

Part Number: AM3359

Hi.

I am trying to connect a parallel NOR over beaglebone black. I used the online TI PINMUX TOOL for that, and connected the NOR correspondingly.

Yet, although I see that the kernel code tries to identify any connected NOR device (I see the code reaching to the send-command functions), it ends up with |

of-flash 8000000.nor: do_map_probe() failed for type cfi_probe

When I connected a logic analyzer on the exported lines, I noticed that WE and OE are toggled simultaneously, and the data bus has incosistent data.

Is there any pinmux file for parallel NOR over beaglbone that is proven to be working?

Thanks.

over 5 years ago

0 Biser Gatchev-XID over 5 years ago

TI__Guru**** 393215 points

Hi,

Please post the Linux version you use, the device tree and pinmux settings.

0 Lior Yaron Benjamin over 5 years ago in reply to Biser Gatchev-XID

Prodigy 170 points

Hi.

I am using linux version 4.14.40. I am not using any SDK, just the linux kernel sources.

The PINMUX information is taken from TI PINMUX TOOL (online), defining a 8bit asynchronous NOR.

my dts file is as follows:

&am33xx_pinmux {
	bbcape_nor_flash_pins: bbcape_nor_flash_pins {
		pinctrl-single,pins = <
 			0x6c (PIN_OUTPUT | MUX_MODE4) /* (V17) gpmc_a11.gpmc_a27 */
 			0x68 (PIN_OUTPUT | MUX_MODE4) /* (T16) gpmc_a10.gpmc_a26 */
 			0x104 (PIN_OUTPUT | MUX_MODE1) /* (G18) mmc0_cmd.gpmc_a25 */
 			0x100 (PIN_OUTPUT | MUX_MODE1) /* (G17) mmc0_clk.gpmc_a24 */
 			0xfc (PIN_OUTPUT | MUX_MODE1) /* (G16) mmc0_dat0.gpmc_a23 */
 			0xf8 (PIN_OUTPUT | MUX_MODE1) /* (G15) mmc0_dat1.gpmc_a22 */
 			0xf4 (PIN_OUTPUT | MUX_MODE1) /* (F18) mmc0_dat2.gpmc_a21 */
 			0xf0 (PIN_OUTPUT | MUX_MODE1) /* (F17) mmc0_dat3.gpmc_a20 */
 			0xdc (PIN_OUTPUT | MUX_MODE1) /* (T5) lcd_data15.gpmc_a19 */
 			0xd8 (PIN_OUTPUT | MUX_MODE1) /* (V4) lcd_data14.gpmc_a18 */
 			0xd4 (PIN_OUTPUT | MUX_MODE1) /* (V3) lcd_data13.gpmc_a17 */
 			0xd0 (PIN_OUTPUT | MUX_MODE1) /* (V2) lcd_data12.gpmc_a16 */
 			0xcc (PIN_OUTPUT | MUX_MODE1) /* (U4) lcd_data11.gpmc_a15 */
 			0xc8 (PIN_OUTPUT | MUX_MODE1) /* (U3) lcd_data10.gpmc_a14 */
 			0xc4 (PIN_OUTPUT | MUX_MODE1) /* (U2) lcd_data9.gpmc_a13 */
 			0xc0 (PIN_OUTPUT | MUX_MODE1) /* (U1) lcd_data8.gpmc_a12 */
 			0xec (PIN_OUTPUT | MUX_MODE1) /* (R6) lcd_ac_bias_en.gpmc_a11 */
 			0xe8 (PIN_OUTPUT | MUX_MODE1) /* (V5) lcd_pclk.gpmc_a10 */
 			0xe4 (PIN_OUTPUT | MUX_MODE1) /* (R5) lcd_hsync.gpmc_a9 */
 			0xe0 (PIN_OUTPUT | MUX_MODE1) /* (U5) lcd_vsync.gpmc_a8 */
 			0xbc (PIN_OUTPUT | MUX_MODE1) /* (T4) lcd_data7.gpmc_a7 */
 			0xb8 (PIN_OUTPUT | MUX_MODE1) /* (T3) lcd_data6.gpmc_a6 */
 			0xb4 (PIN_OUTPUT | MUX_MODE1) /* (T2) lcd_data5.gpmc_a5 */
 			0xb0 (PIN_OUTPUT | MUX_MODE1) /* (T1) lcd_data4.gpmc_a4 */
 			0xac (PIN_OUTPUT | MUX_MODE1) /* (R4) lcd_data3.gpmc_a3 */
 			0xa8 (PIN_OUTPUT | MUX_MODE1) /* (R3) lcd_data2.gpmc_a2 */
 			0xa4 (PIN_OUTPUT | MUX_MODE1) /* (R2) lcd_data1.gpmc_a1 */
 			0xa0 (PIN_OUTPUT | MUX_MODE1) /* (R1) lcd_data0.gpmc_a0 */

 			0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* (T9) gpmc_ad7.gpmc_ad7 */
 			0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* (R9) gpmc_ad6.gpmc_ad6 */
 			0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* (V8) gpmc_ad5.gpmc_ad5 */
 			0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* (U8) gpmc_ad4.gpmc_ad4 */
 			0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* (T8) gpmc_ad3.gpmc_ad3 */
 			0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* (R8) gpmc_ad2.gpmc_ad2 */
 			0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* (V7) gpmc_ad1.gpmc_ad1 */
 			0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* (U7) gpmc_ad0.gpmc_ad0 */
 			
 			0x70 (PIN_INPUT | MUX_MODE0) /* (T17) gpmc_wait0.gpmc_wait0 */
 			0x8c (PIN_INPUT | MUX_MODE2) /* (V12) gpmc_clk.gpmc_wait1 */
 			0x74 (PIN_OUTPUT | MUX_MODE0) /* (U17) gpmc_wpn.gpmc_wpn */
 			0x78 (PIN_OUTPUT | MUX_MODE0) /* (U18) gpmc_be1n.gpmc_be1n */
 			0x94 (PIN_OUTPUT | MUX_MODE0) /* (T7) gpmc_oen_ren.gpmc_oen_ren */
 			0x98 (PIN_OUTPUT | MUX_MODE0) /* (U6) gpmc_wen.gpmc_wen */
 			0x7c (PIN_OUTPUT | MUX_MODE0) /* (V6) gpmc _csn0.gpmc_csn0 */
		>;
	};
};

&elm {
	status = "okay";
};

&gpmc {
  status = "okay";
	ranges = <0 0 0x08000000 0x01000000>;	/* address offset=128MB, range=128Mb=16MB */
  nor@0,0 {
    compatible = "cfi-flash";
		reg = <0 0 0x01000000>;		/* device memory map = actual device size = 16MB */
/*		pinctrl-names = "default";*/
		pinctrl-0 = <&bbcape_nor_flash_pins>;
		bank-width = <1>;
		/* vendor specific bindings */
		gpmc,device-width = <2>;
		gpmc,mux-add-data = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <120>;
		gpmc,cs-wr-off-ns = <120>;
		gpmc,adv-on-ns = <10>;
		gpmc,adv-rd-off-ns = <40>;
		gpmc,adv-wr-off-ns = <40>;
		gpmc,we-on-ns = <50>;
		gpmc,we-off-ns = <120>;
		gpmc,oe-on-ns = <50>;
		gpmc,oe-off-ns = <120>;
		gpmc,access-ns = <100>;
		gpmc,rd-cycle-ns = <120>;
		gpmc,wr-cycle-ns = <120>;
		gpmc,page-burst-access-ns = <0>;
		gpmc,cycle2cycle-samecsen;
		gpmc,num-waitpins = <4>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <20>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-access-ns = <80>;
		gpmc,wr-data-mux-bus-ns = <100>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		* which can be independently programmable */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0x00000000 {
			label = "NOR.SPL";
			reg = <0x00000000 0x00040000>;
		};
		partition@0x00040000 {
			label = "NOR.SPL.backup1";
			reg = <0x00040000 0x00040000>;
		};
		partition@0x00080000 {
			label = "NOR.SPL.backup2";
			reg = <0x00080000 0x00040000>;
		};
		partition@0x000c0000 {
			label = "NOR.SPL.backup3";
			reg = <0x000c0000 0x00040000>;
		};
		partition@0x00100000 {
			label = "NOR.u-boot-spl-os";
			reg = <0x00100000 0x00080000>;
		};
		partition@0x00180000 {
			label = "NOR.u-boot";
			reg = <0x00180000 0x00100000>;
		};
		partition@0x00280000 {
			label = "NOR.u-boot-env";
			reg = <0x00280000 0x00040000>;
		};
		partition@0x002c0000 {
			label = "NOR.u-boot-env.backup1";
			reg = <0x002c0000 0x00040000>;
		};
		partition@0x00300000 {
			label = "NOR.kernel";
			reg = <0x00300000 0x00700000>;
		};
		partition@0x00a00000 {
			label = "NOR.file-system";
			reg = <0x00a00000 0x00600000>;		
		};
	};
};

Thanks.

&am33xx_pinmux { bbcape_nor_flash_pins: bbcape_nor_flash_pins { pinctrl-single,pins = < 0x6c (PIN_OUTPUT | MUX_MODE4) /* (V17) gpmc_a11.gpmc_a27 */ 0x68 (PIN_OUTPUT | MUX_MODE4) /* (T16) gpmc_a10.gpmc_a26 */ 0x104 (PIN_OUTPUT | MUX_MODE1) /* (G18) mmc0_cmd.gpmc_a25 */ 0x100 (PIN_OUTPUT | MUX_MODE1) /* (G17) mmc0_clk.gpmc_a24 */ 0xfc (PIN_OUTPUT | MUX_MODE1) /* (G16) mmc0_dat0.gpmc_a23 */ 0xf8 (PIN_OUTPUT | MUX_MODE1) /* (G15) mmc0_dat1.gpmc_a22 */ 0xf4 (PIN_OUTPUT | MUX_MODE1) /* (F18) mmc0_dat2.gpmc_a21 */ 0xf0 (PIN_OUTPUT | MUX_MODE1) /* (F17) mmc0_dat3.gpmc_a20 */ 0xdc (PIN_OUTPUT | MUX_MODE1) /* (T5) lcd_data15.gpmc_a19 */ 0xd8 (PIN_OUTPUT | MUX_MODE1) /* (V4) lcd_data14.gpmc_a18 */ 0xd4 (PIN_OUTPUT | MUX_MODE1) /* (V3) lcd_data13.gpmc_a17 */ 0xd0 (PIN_OUTPUT | MUX_MODE1) /* (V2) lcd_data12.gpmc_a16 */ 0xcc (PIN_OUTPUT | MUX_MODE1) /* (U4) lcd_data11.gpmc_a15 */ 0xc8 (PIN_OUTPUT | MUX_MODE1) /* (U3) lcd_data10.gpmc_a14 */ 0xc4 (PIN_OUTPUT | MUX_MODE1) /* (U2) lcd_data9.gpmc_a13 */ 0xc0 (PIN_OUTPUT | MUX_MODE1) /* (U1) lcd_data8.gpmc_a12 */ 0xec (PIN_OUTPUT | MUX_MODE1) /* (R6) lcd_ac_bias_en.gpmc_a11 */ 0xe8 (PIN_OUTPUT | MUX_MODE1) /* (V5) lcd_pclk.gpmc_a10 */ 0xe4 (PIN_OUTPUT | MUX_MODE1) /* (R5) lcd_hsync.gpmc_a9 */ 0xe0 (PIN_OUTPUT | MUX_MODE1) /* (U5) lcd_vsync.gpmc_a8 */ 0xbc (PIN_OUTPUT | MUX_MODE1) /* (T4) lcd_data7.gpmc_a7 */ 0xb8 (PIN_OUTPUT | MUX_MODE1) /* (T3) lcd_data6.gpmc_a6 */ 0xb4 (PIN_OUTPUT | MUX_MODE1) /* (T2) lcd_data5.gpmc_a5 */ 0xb0 (PIN_OUTPUT | MUX_MODE1) /* (T1) lcd_data4.gpmc_a4 */ 0xac (PIN_OUTPUT | MUX_MODE1) /* (R4) lcd_data3.gpmc_a3 */ 0xa8 (PIN_OUTPUT | MUX_MODE1) /* (R3) lcd_data2.gpmc_a2 */ 0xa4 (PIN_OUTPUT | MUX_MODE1) /* (R2) lcd_data1.gpmc_a1 */ 0xa0 (PIN_OUTPUT | MUX_MODE1) /* (R1) lcd_data0.gpmc_a0 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* (T9) gpmc_ad7.gpmc_ad7 */ 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* (R9) gpmc_ad6.gpmc_ad6 */ 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* (V8) gpmc_ad5.gpmc_ad5 */ 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* (U8) gpmc_ad4.gpmc_ad4 */ 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* (T8) gpmc_ad3.gpmc_ad3 */ 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* (R8) gpmc_ad2.gpmc_ad2 */ 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* (V7) gpmc_ad1.gpmc_ad1 */ 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* (U7) gpmc_ad0.gpmc_ad0 */ 0x70 (PIN_INPUT | MUX_MODE0) /* (T17) gpmc_wait0.gpmc_wait0 */ 0x8c (PIN_INPUT | MUX_MODE2) /* (V12) gpmc_clk.gpmc_wait1 */ 0x74 (PIN_OUTPUT | MUX_MODE0) /* (U17) gpmc_wpn.gpmc_wpn */ 0x78 (PIN_OUTPUT | MUX_MODE0) /* (U18) gpmc_be1n.gpmc_be1n */ 0x94 (PIN_OUTPUT | MUX_MODE0) /* (T7) gpmc_oen_ren.gpmc_oen_ren */ 0x98 (PIN_OUTPUT | MUX_MODE0) /* (U6) gpmc_wen.gpmc_wen */ 0x7c (PIN_OUTPUT | MUX_MODE0) /* (V6) gpmc _csn0.gpmc_csn0 */ >; };};
&elm { status = "okay";};
&gpmc { status = "okay"; ranges = <0 0 0x08000000 0x01000000>; /* address offset=128MB, range=128Mb=16MB */ nor@0,0 { compatible = "cfi-flash"; reg = <0 0 0x01000000>; /* device memory map = actual device size = 16MB *//* pinctrl-names = "default";*/ pinctrl-0 = <&bbcape_nor_flash_pins>; bank-width = <1>; /* vendor specific bindings */ gpmc,device-width = <2>; gpmc,mux-add-data = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <120>; gpmc,cs-wr-off-ns = <120>; gpmc,adv-on-ns = <10>; gpmc,adv-rd-off-ns = <40>; gpmc,adv-wr-off-ns = <40>; gpmc,we-on-ns = <50>; gpmc,we-off-ns = <120>; gpmc,oe-on-ns = <50>; gpmc,oe-off-ns = <120>; gpmc,access-ns = <100>; gpmc,rd-cycle-ns = <120>; gpmc,wr-cycle-ns = <120>; gpmc,page-burst-access-ns = <0>; gpmc,cycle2cycle-samecsen; gpmc,num-waitpins = <4>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <20>; gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <80>; gpmc,wr-data-mux-bus-ns = <100>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable */ #address-cells = <1>; #size-cells = <1>; partition@0x00000000 { label = "NOR.SPL"; reg = <0x00000000 0x00040000>; }; partition@0x00040000 { label = "NOR.SPL.backup1"; reg = <0x00040000 0x00040000>; }; partition@0x00080000 { label = "NOR.SPL.backup2"; reg = <0x00080000 0x00040000>; }; partition@0x000c0000 { label = "NOR.SPL.backup3"; reg = <0x000c0000 0x00040000>; }; partition@0x00100000 { label = "NOR.u-boot-spl-os"; reg = <0x00100000 0x00080000>; }; partition@0x00180000 { label = "NOR.u-boot"; reg = <0x00180000 0x00100000>; }; partition@0x00280000 { label = "NOR.u-boot-env"; reg = <0x00280000 0x00040000>; }; partition@0x002c0000 { label = "NOR.u-boot-env.backup1"; reg = <0x002c0000 0x00040000>; }; partition@0x00300000 { label = "NOR.kernel"; reg = <0x00300000 0x00700000>; }; partition@0x00a00000 { label = "NOR.file-system"; reg = <0x00a00000 0x00600000>; }; };};

0 RonB over 5 years ago in reply to Lior Yaron Benjamin

TI__Mastermind 30276 points

Lior,

Looking through the kernel sources, there is a file, am335x-nano.dts that has a NOR node that should be a good reference for you. Also, looking at the bindings document at memory-controllers/omap-gpmc.txt, you seem to be missing several required nodes that should be added to your gpmc node.

Also, grepping the sources for the errors you are getting back and adding printfs to get more details is a great way to learn what the driver expects and how to provide it.

I hope this is helpful to you.

0 Lior Yaron Benjamin over 5 years ago in reply to RonB

Prodigy 170 points

Thanks for your reply, Ron.

The am335x-nano.dts file is the one I tried to use in my device tree.

Moreover, I also tried to use the omap-gpmc.txt as an example. That exact GPMC node was used before to activate a NAND device, and now I want to try using a NOR device.
Unfortunately, the only error I get is that a device was not found. I tried to connect external logic analyzer, and I noticed that the lines are now not active at all.
That is why I suspect my pinmux configuration is incorrect.

Has anyone has a working pinmux file?

0 RonB over 5 years ago in reply to Lior Yaron Benjamin

TI__Mastermind 30276 points

LIor,

I'm sorry I don't have a verified NOR pin mux file as we don't have a supported board with NOR.

In your file, I believe the pinctrl needs to be under the gpmc node, not the nor child node. Have you tried that?

0 Lior Yaron Benjamin over 5 years ago in reply to RonB

Prodigy 170 points

Well, after a while I am back with that issue.
I fixed the device-tree, and the config file, and now I do see that the beaglebone is trying to to probe the NOR chip.

Yet, the probe fails.
I am using a NOR chip that expects command 0x98 and address 0xaa to enter CFI mode (8bits data). The kernel code tries all known commands, including that one, but on output lines (using logic analyzer), I observed a wierd issue:
When sending the 0x98 command with address 0x55 (which my NOR should not answer that), all signals looks fine. Yet, when I send the command 0x98 with address 0xaa, the WE command is not triggered.
While trying to understand what's going on, I noticed that, when bit 8 of the address is set, the WE is not triggered. i.e. - all addresses 0x00-0x7f trigger WE, address 0x80-0xff doesn't, adreses 0x100-0x17f do trigger, and again 0x180-0x1ff doesn't, and so on.

My device-tree is attached below.

Do you have any idea what can cause such a weird behavior?
Thanks.

&am33xx_pinmux {
	bbcape_nor_flash_pins: bbcape_nor_flash_pins {
		pinctrl-single,pins = <
 			0x6c (PIN_OUTPUT | MUX_MODE4) /* (V17) gpmc_a11.gpmc_a27 */
 			0x68 (PIN_OUTPUT | MUX_MODE4) /* (T16) gpmc_a10.gpmc_a26 */
 			0x104 (PIN_OUTPUT | MUX_MODE1) /* (G18) mmc0_cmd.gpmc_a25 */
 			0x100 (PIN_OUTPUT | MUX_MODE1) /* (G17) mmc0_clk.gpmc_a24 */
 			0xfc (PIN_OUTPUT | MUX_MODE1) /* (G16) mmc0_dat0.gpmc_a23 */
 			0xf8 (PIN_OUTPUT | MUX_MODE1) /* (G15) mmc0_dat1.gpmc_a22 */
 			0xf4 (PIN_OUTPUT | MUX_MODE1) /* (F18) mmc0_dat2.gpmc_a21 */
 			0xf0 (PIN_OUTPUT | MUX_MODE1) /* (F17) mmc0_dat3.gpmc_a20 */
 			0xdc (PIN_OUTPUT | MUX_MODE1) /* (T5) lcd_data15.gpmc_a19 */
 			0xd8 (PIN_OUTPUT | MUX_MODE1) /* (V4) lcd_data14.gpmc_a18 */
 			0xd4 (PIN_OUTPUT | MUX_MODE1) /* (V3) lcd_data13.gpmc_a17 */
 			0xd0 (PIN_OUTPUT | MUX_MODE1) /* (V2) lcd_data12.gpmc_a16 */
 			0xcc (PIN_OUTPUT | MUX_MODE1) /* (U4) lcd_data11.gpmc_a15 */
 			0xc8 (PIN_OUTPUT | MUX_MODE1) /* (U3) lcd_data10.gpmc_a14 */
 			0xc4 (PIN_OUTPUT | MUX_MODE1) /* (U2) lcd_data9.gpmc_a13 */
 			0xc0 (PIN_OUTPUT | MUX_MODE1) /* (U1) lcd_data8.gpmc_a12 */
 			0xec (PIN_OUTPUT | MUX_MODE1) /* (R6) lcd_ac_bias_en.gpmc_a11 */
 			0xe8 (PIN_OUTPUT | MUX_MODE1) /* (V5) lcd_pclk.gpmc_a10 */
 			0xe4 (PIN_OUTPUT | MUX_MODE1) /* (R5) lcd_hsync.gpmc_a9 */
 			0xe0 (PIN_OUTPUT | MUX_MODE1) /* (U5) lcd_vsync.gpmc_a8 */
 			0xbc (PIN_OUTPUT | MUX_MODE1) /* (T4) lcd_data7.gpmc_a7 */
 			0xb8 (PIN_OUTPUT | MUX_MODE1) /* (T3) lcd_data6.gpmc_a6 */
 			0xb4 (PIN_OUTPUT | MUX_MODE1) /* (T2) lcd_data5.gpmc_a5 */
 			0xb0 (PIN_OUTPUT | MUX_MODE1) /* (T1) lcd_data4.gpmc_a4 */
 			0xac (PIN_OUTPUT | MUX_MODE1) /* (R4) lcd_data3.gpmc_a3 */
 			0xa8 (PIN_OUTPUT | MUX_MODE1) /* (R3) lcd_data2.gpmc_a2 */
 			0xa4 (PIN_OUTPUT | MUX_MODE1) /* (R2) lcd_data1.gpmc_a1 */
 			0xa0 (PIN_OUTPUT | MUX_MODE1) /* (R1) lcd_data0.gpmc_a0 */

 			0x1c (PIN_INPUT | MUX_MODE0) /* (T9) gpmc_ad7.gpmc_ad7 */
 			0x18 (PIN_INPUT | MUX_MODE0) /* (R9) gpmc_ad6.gpmc_ad6 */
 			0x14 (PIN_INPUT | MUX_MODE0) /* (V8) gpmc_ad5.gpmc_ad5 */
 			0x10 (PIN_INPUT | MUX_MODE0) /* (U8) gpmc_ad4.gpmc_ad4 */
 			0xc (PIN_INPUT | MUX_MODE0) /* (T8) gpmc_ad3.gpmc_ad3 */
 			0x8 (PIN_INPUT | MUX_MODE0) /* (R8) gpmc_ad2.gpmc_ad2 */
 			0x4 (PIN_INPUT | MUX_MODE0) /* (V7) gpmc_ad1.gpmc_ad1 */
 			0x0 (PIN_INPUT | MUX_MODE0) /* (U7) gpmc_ad0.gpmc_ad0 */

 			0x70 (PIN_INPUT | MUX_MODE0) /* (T17) gpmc_wait0.gpmc_wait0 */
 			0x8c (PIN_INPUT | MUX_MODE2) /* (V12) gpmc_clk.gpmc_wait1 */
 			0x74 (PIN_OUTPUT | MUX_MODE0) /* (U17) gpmc_wpn.gpmc_wpn */
 			0x78 (PIN_OUTPUT | MUX_MODE0) /* (U18) gpmc_be1n.gpmc_be1n */
 			0x94 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (T7) gpmc_oen_ren.gpmc_oen_ren */
 			0x98 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (U6) gpmc_wen.gpmc_wen */
 			0x7c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (V6) gpmc _csn0.gpmc_csn0 */
		>;
	};
};

&elm {
	status = "okay";
};

&gpmc {
  status = "okay";
	ti,hwmods = "gpmc";
	interrupts = <20>;
	gpmc,num-cs = <8>;
	gpmc,num-waitpins = <4>;
	#address-cells = <2>;
	#size-cells = <1>;

	ranges = <0 0 0x08000000 0x08000000>;

	nor@0,0 {
		compatible = "cfi-flash";
		pinctrl-names = "default";
		pinctrl-0 = <&bbcape_nor_flash_pins>;
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0 0x08000000>;
		bank-width = <1>;

		gpmc,mux-add-data;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <186>;
		gpmc,cs-wr-off-ns = <186>;
		gpmc,adv-on-ns = <12>;
		gpmc,adv-rd-off-ns = <48>;
		gpmc,adv-wr-off-ns = <48>;
		gpmc,oe-on-ns = <54>;
		gpmc,oe-off-ns = <168>;
		gpmc,we-on-ns = <54>;
		gpmc,we-off-ns = <168>;
		gpmc,rd-cycle-ns = <186>;
		gpmc,wr-cycle-ns = <186>;
		gpmc,access-ns = <114>;
		gpmc,page-burst-access-ns = <6>;
		gpmc,bus-turnaround-ns = <12>;
		gpmc,cycle2cycle-delay-ns = <18>;
		gpmc,wr-data-mux-bus-ns = <90>;
		gpmc,wr-access-ns = <186>;
		gpmc,cycle2cycle-samecsen;
		gpmc,cycle2cycle-diffcsen;

		partition@0 {
			label = "bootloader-nor";
			reg = <0 0x40000>;
		};
		partition@0x40000 {
			label = "params-nor";
			reg = <0x40000 0x40000>;
		};
		partition@0x80000 {
			label = "kernel-nor";
			reg = <0x80000 0x200000>;
		};
		partition@0x280000 {
			label = "filesystem-nor";
			reg = <0x240000 0x7d80000>;
		};
	};
};

0 Lior Yaron Benjamin over 5 years ago in reply to Lior Yaron Benjamin

Prodigy 170 points

Please ignore my last update.

0 Lior Yaron Benjamin over 5 years ago in reply to Lior Yaron Benjamin

Prodigy 170 points

OK.
So the correct current status is as follows:
I am using a NOR chip that expects command 0x98 and address 0xaa to enter CFI mode (8bits data). The kernel code tries all known commands, including that one, but the control lines are not triggered.

The pinmux is as described above

0 RonB over 5 years ago in reply to Lior Yaron Benjamin

TI__Mastermind 30276 points

Lior,

Could you please clarify "the control lines are not triggered"? Does the command go to the flash?

Thanks.

0 Lior Yaron Benjamin over 5 years ago in reply to RonB

Prodigy 170 points

Hi Ron.

I see the address and data signals toggling correctly, but CS and WE are not toggled. OE does toggle.

Thanks

0 RonB over 5 years ago in reply to Lior Yaron Benjamin

TI__Mastermind 30276 points

Lior,

Thanks for clarifying. I found a reference for the pinmux here:

patchwork.kernel.org/.../

Maybe that has something useful for you.

0 Lior Yaron Benjamin over 5 years ago in reply to RonB

Prodigy 170 points

Hi Ron.

Thanks for your help.
Apparently, I had several issues:
* reg entity:

reg = <0 0 0x01000000>;

Originally I tried to use 0x08000000 and it cause alignment issues, while the driver can't handle.

* timing issues

some of my timing definitions where in correct

but apparently, the worse issue was that my test equipment, my logic analyzer, did not work correctly, and completely misses signals toggling.

Any way, I now have a working setup with NOR connected to BBB. It required disabling both mmc0 and one of the user leds , and also moving mmc1 to an alternate pin configuration, but now it works.

Thanks again

0 RonB over 5 years ago in reply to Lior Yaron Benjamin

TI__Mastermind 30276 points

Lior,

Thanks for reporting back and sharing some of your fixes.

Processors

Processors forum

AM3359: Parallel NOR over BeagelBone black