Linux/AM5728: GPMC EDMA causes kernel panic (kernel version 4.1.13)

Hi, This is based on the Phytec 15.1-rc4 RDK. Here are the relevant snippets pertinent to the edma and gpmc nodes:

edma: edma-controller@43300000 {
    compatible = "ti,edma3";
    reg = <0x43300000 0x801c>;
    interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
    #dma-cells = <1>;
    ti,hwmods = "tpcc", "tptc0", "tptc1";
    dma-requests = <64>;
};

edma_xbar: dma-router@4a002c78 {
    compatible = "ti,dra7-dma-crossbar";
    reg = <0x4a002c78 0x7c>;
    #dma-cells = <1>;
    dma-requests = <204>;
    ti,dma-safe-map = <0>;
    dma-masters = <&edma>;
};

gpmc: gpmc@50000000 {
    compatible = "ti,am3352-gpmc";
    ti,hwmods = "gpmc";
    reg = <0x50000000 0x2000>;      /* device IO registers */
    interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    dmas = <&edma_xbar 4>;
    dma-names = "rxtx";
    gpmc,num-cs = <8>;
    gpmc,num-waitpins = <2>;
    #address-cells = <2>;
    #size-cells = <1>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    status = "disabled";
};

fpga_pins_default: fpga_pins_default {
    pinctrl-single,pins = <
                0x000 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad0.gpmc_ad0 MODE0 | INPUT | PULLUP */
                0x004 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad1.gpmc_ad1 MODE0 | INPUT | PULLUP */
                0x008 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad2.gpmc_ad2 MODE0 | INPUT | PULLUP */
                0x00C (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad3.gpmc_ad3 MODE0 | INPUT | PULLUP */
                0x010 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad4.gpmc_ad4 MODE0 | INPUT | PULLUP */
                0x014 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad5.gpmc_ad5 MODE0 | INPUT | PULLUP */
                0x018 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad6.gpmc_ad6 MODE0 | INPUT | PULLUP */
                0x01C (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad7.gpmc_ad7 MODE0 | INPUT | PULLUP */
                0x020 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad8.gpmc_ad8 MODE0 | INPUT | PULLUP */
                0x024 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad9.gpmc_ad9 MODE0 | INPUT | PULLUP */
                0x028 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad10.gpmc_ad10 MODE0 | INPUT | PULLUP */
                0x02C (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad11.gpmc_ad11 MODE0 | INPUT | PULLUP */
                0x030 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad12.gpmc_ad12 MODE0 | INPUT | PULLUP */
                0x034 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad13.gpmc_ad13 MODE0 | INPUT | PULLUP */
                0x038 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad14.gpmc_ad14 MODE0 | INPUT | PULLUP */
                0x03C (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad15.gpmc_ad15 MODE0 | INPUT | PULLUP */

                0x0BC (PIN_OUTPUT | MUX_MODE0)            /* gpmc_cs3.gpmc_cs3 MODE0 | OUTPUT */

                0x0C0 (PIN_INPUT | MUX_MODE0)           /* gpmc_clk.gpmc_clk MODE0 | INPUT */
                0x0C4 (PIN_OUTPUT | MUX_MODE0)          /* gpmc_advn_ale.gpmc_advn_ale MODE0 | OUTPUT */
                0x0C8 (PIN_OUTPUT | MUX_MODE0)            /* gpmc_oen_ren.gpmc_oen_ren MODE0 | OUTPUT */
                0x0CC (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen MODE0 | OUTPUT */
                0x0D0 (PIN_OUTPUT | MUX_MODE0)          /* gpmc_ben0_cle.gpmc_ben0_cle MODE0 | OUTPUT */
                0x0D4 (PIN_OUTPUT | MUX_MODE0)            /* gpmc_ben1_cle.gpmc_ben1_cle MODE0 | OUTPUT */
                0x0D8 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_wait0.gpmc_wait0 MODE0 | INPUT | PULLUP */
        0x5C  (PIN_INPUT_PULLUP | MUX_MODE14)    /* gpio1_29 */
    >;
};


&gpmc {
    pinctrl-names="default";
    pinctrl-0 = <&fpga_pins_default>;
    ranges = <3 0 0x3000000 0x0100000>; /* fpga */

    hs_gpmc: fpga@3,0 {
        reg = <3 0 0x100000>;

        #address-cells = <1>;
        #size-cells = <1>;
        interrupt-parent = <&gpio1>;
        interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
        compatible = "lgs,hs-fpga";

        bank-width = <2>;

        gpmc,sync-clk-ps = <0>; /* Minimum clock period for synchronous mode, in picoseconds */

        gpmc,cs-on-ns = <0>; /* Assertion time */
        gpmc,cs-rd-off-ns = <100> ; /* Read deassertion time */
        gpmc,cs-wr-off-ns = <40>; /* Write deassertion time */

        /* ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: */
        gpmc,adv-on-ns = <0>; /* Assertion time */
        gpmc,adv-rd-off-ns = <20>; /* Read deassertion time */
        gpmc,adv-wr-off-ns = <20>; /* Write deassertion time */

        /* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,we-on-ns = <20>; /* Assertion time */
        gpmc,we-off-ns = <20>; /* Deassertion time */
    
        /* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,oe-on-ns = <20>; /* Assertion time */
        gpmc,oe-off-ns = <100>; /* Deassertion time */

        /* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
        gpmc,page-burst-access-ns = <20>; /* Multiple access word delay */
        gpmc,access-ns = <10>; /* Start-cycle to first data valid delay */
        gpmc,rd-cycle-ns = <20>; /* Total read cycle time */
        gpmc,wr-cycle-ns = <10>; /* Total write cycle time */

        gpmc,device-width = <2>; /* Total width of device(s) connected to a GPMC
        chip-select in bytes. The GPMC supports 8-bit
        and 16-bit devices and so this property must be
        1 or 2. */

        gpmc,sync-read = <1>; /* Enables synchronous read. Defaults to asynchronous
        is this is not set. */
        gpmc,sync-write = <1>; /* Enables synchronous writes. Defaults to asynchronous
        is this is not set. */
        gpmc,data-mux-bus = <1>;
    };
};

Unfortunately, we can't disable the McSPI interface as that is another interface we use to communicate with the FPGA and ultimately trigger the DMA transaction. Is there anything that you can suggest we try?

The specific error was resolved by selecting the appropriate in our "child" driver dts specification (we needed to specificy edma_xbar 4 as the dma device and "rxtx" as the name. However, when specifying this and using dma_request_slave_channel(&pdev->dev, "rxtx"), we're not getting any GPMC transactions.

The specific error was resolved by selecting the appropriate in our "child" driver dts specification (we needed to specificy edma_xbar 4 as the dma device and "rxtx" as the name

Attached is the updated node for our custom gpmc device that prevented the kernel panic, but it also seems that the GPMC transaction isn't being triggered as well.

hs_gpmc: fpga@3,0 {
        reg = <3 0 0x100000>;

        #address-cells = <1>;
        #size-cells = <1>;
        interrupt-parent = <&gpio1>;
        interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
        dmas = <&edma_xbar 4>;
        dma-names = "rxtx";
        compatible = "lgs,hs-fpga";

        bank-width = <2>;

        gpmc,sync-clk-ps = <0>; /* Minimum clock period for synchronous mode, in picoseconds */

        gpmc,cs-on-ns = <0>; /* Assertion time */
        gpmc,cs-rd-off-ns = <100> ; /* Read deassertion time */
        gpmc,cs-wr-off-ns = <40>; /* Write deassertion time */

        /* ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: */
        gpmc,adv-on-ns = <0>; /* Assertion time */
        gpmc,adv-rd-off-ns = <20>; /* Read deassertion time */
        gpmc,adv-wr-off-ns = <20>; /* Write deassertion time */

        /* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,we-on-ns = <20>; /* Assertion time */
        gpmc,we-off-ns = <20>; /* Deassertion time */
    
        /* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,oe-on-ns = <20>; /* Assertion time */
        gpmc,oe-off-ns = <100>; /* Deassertion time */

        /* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
        gpmc,page-burst-access-ns = <20>; /* Multiple access word delay */
        gpmc,access-ns = <10>; /* Start-cycle to first data valid delay */
        gpmc,rd-cycle-ns = <20>; /* Total read cycle time */
        gpmc,wr-cycle-ns = <10>; /* Total write cycle time */

        gpmc,device-width = <2>; /* Total width of device(s) connected to a GPMC
        chip-select in bytes. The GPMC supports 8-bit
        and 16-bit devices and so this property must be
        1 or 2. */

        gpmc,sync-read = <1>; /* Enables synchronous read. Defaults to asynchronous
        is this is not set. */
        gpmc,sync-write = <1>; /* Enables synchronous writes. Defaults to asynchronous
        is this is not set. */
        gpmc,data-mux-bus = <1>;
    };

Hi,

Thanks for getting back to me. Unfortunately, even if I remove the dma_xbar entries in the "hs_gpmc" dts node, I still don't see any transactions.

Here is where I set the source address in the DMA engine:

memset(&data->cfg, 0, sizeof(data->cfg));
data->cfg.direction = DMA_DEV_TO_MEM;
data->cfg.src_addr = HS_GPMC_FPGA_DMA_START_ADDRESS;
data->cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
data->cfg.src_maxburst = 2
dmaengine_slave_config(data->chan, &data->cfg);

where HS_GPMC_FPGA_DMA_START_ADDRESS is hard-coded 0x3000000 (set from the DTS)

Here is where I set up the underlying eDMA driver for a single transaction and issue the request:

tx_sync_desc = dmaengine_prep_slave_single(data->chan, data->dma_start, HS_GPMC_FPGA_LEN, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
tx_sync_desc->callback = hs_gpmc_fpga_dma_callback;
tx_sync_desc->callback_param = data;

dma_cookie = dmaengine_submit(tx_sync_desc);
dma_async_issue_pending(data->chan);

I can see that the appropriate call gets made in the underlying edma driver to kick off the DMA (here are some printks from my driver and the eDMA driver):

[  223.977816] hs_gpmc_irq_handler: Going to start DMA transaction
[  223.983763] MO MO MO: edma_prep_slave_sg dir 2 flags 1
[  223.988923] MO MO MO: edma_prep_slave_sg dev to mem src addr: 0x3000000 width = 4
[  223.996437] MO MO MO: Prepped slave single
[  224.000548] MO MO MO : submitted dma request
[  224.004833] MO MO MO: going to execute edma
[  224.009035] MO MO MO: going to restore irq
[  224.013145] MO MO MO: issued pending request
[  224.017440] MO MO MO: returning from irq handler

but the GPMC transaction never happens and my DMA callback is never called.

Thanks

Mohammed

Hi,

Sorry about that. Yes, we do set it in the main DTS file:

&gpmc {
        status = "okay";
};


We have tried asynchronous GPMC and that works fine, but we need to use the DMA for our synchronous (high-speed) GPMC transactions.

I applied the GPMC timing settings to the DTS as per the instructions in the TRM:

gpmc,sync-clk-ps = <15152>; /* Minimum clock period for synchronous mode, in picoseconds */

		gpmc,cs-on-ns = <0>; /* Assertion time */
		/*gpmc,cs-rd-off-ns = <100> ; /* Read deassertion time */*/
		gpmc,cs-rd-off-ns = <470> ; /* Read deassertion time */
		gpmc,cs-wr-off-ns = <40>; /* Write deassertion time */
		gpmc,burst-read; /* burst read */
		gpmc,burst-length = <8>; /* Attached device page length */

		/* ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: */
		gpmc,adv-on-ns = <0>; /* Assertion time */
		/*gpmc,adv-rd-off-ns = <20>; /* Read deassertion time */*/
		gpmc,adv-rd-off-ns = <15>; /* Read deassertion time */
		gpmc,adv-wr-off-ns = <20>; /* Write deassertion time */

		/* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
		gpmc,we-on-ns = <20>; /* Assertion time */
		gpmc,we-off-ns = <20>; /* Deassertion time */
	
		/* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
		/*gpmc,oe-on-ns = <20>; /* Assertion time */*/
		/*gpmc,oe-off-ns = <100>; /* Deassertion time */*/
		gpmc,oe-on-ns = <106>; /* Assertion time */
		gpmc,oe-off-ns = <470>; /* Deassertion time */

		/* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
		/*gpmc,page-burst-access-ns = <20>; /* Multiple access word delay */*/
		gpmc,page-burst-access-ns = <15>; /* Multiple access word delay */
		/*gpmc,access-ns = <10>; /* Start-cycle to first data valid delay */*/
		gpmc,access-ns = <23>; /* Start-cycle to first data valid delay */
		/*gpmc,rd-cycle-ns = <20>; /* Total read cycle time */*/
		gpmc,rd-cycle-ns = <470>; /* Total read cycle time */
		gpmc,wr-cycle-ns = <10>; /* Total write cycle time */

		gpmc,device-width = <2>; /* Total width of device(s) connected to a GPMC
		chip-select in bytes. The GPMC supports 8-bit
		and 16-bit devices and so this property must be
		1 or 2. */

		gpmc,sync-read; /* Enables synchronous read. Defaults to asynchronous
		is this is not set. */
		gpmc,sync-write; /* Enables synchronous writes. Defaults to asynchronous
		is this is not set. */

However, when I boot the kernel, the clock rate that is seen by the GPMC driver is 266 MHz (printk in gpmc_get_fclk_period):

[    4.995171] MO MO MO: rate = 3759l

However, according to the AM5728 TRM, the default L3_clk (and in turn the GPMC clk) should be 166 MHz. The driver is "seeing" a clock rate that is twice the default. We haven't touched the clock rate of the L3 in the DTS.