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Part Number: 66AK2H14
1. How to partition the DDR3A and DDR3B memory across the ARM and DSP cores in Keystone II devices?
The EMIF for DDR3A being attached directly to MSMC has a number of advantages for both ARM and DSP cores:
1) It is closer (lower read latency) than DDR3B for all of them, offering definite performance advantages. It is also a much high bandwidth connection through MSMC.
2) DDR3A supports a larger physical address space of 8GB compared to 2GB for DDR3B. This allows users to alllocate larger private and shared spaces.
3) For ARM cores, there is the added benefit of IO/DMA coherence when using DDR3A.
4) The non-core masters on the device can be configured to access upto 2GB in any part of the 8GB DDR3A space, as opposed to a fixed 512MB on DDR3B.
From a superset platform perspective, DDR3B exists for two reasons:
1) Provide support for wireless co-processors that use small and random accesses that are naturally less efficient for DDR3 EMIFs. This inefficient bandwidth use can be offloaded from DDR3A when using DDR3B.
2) The data being stored there was going to be used by other co-processors instead of the cores which are further away from DDR3B and closer to DDR3A.
2. Are cache coherent maintained by hardware across the A15 and C66x cores?
MSMC does not support memory coherence for these spaces:
The DDR3B then has the following coherent masters and support:
To address the most common mistakes on AK2H processors.
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