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[FAQ] 66AK2H14: DDR3A vs. DDR3B and Cache Coherence on Keystone II devices

Mastermind 31540 points

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Part Number: 66AK2H14

1. How to partition the DDR3A and DDR3B memory across the ARM and DSP cores in Keystone II devices?

The EMIF for DDR3A being attached directly to MSMC has a number of advantages for both ARM and DSP cores:

1) It is closer (lower read latency) than DDR3B for all of them, offering definite performance advantages. It is also a much high bandwidth connection through MSMC.

2) DDR3A supports a larger physical address space of 8GB compared to 2GB for DDR3B. This allows users to alllocate larger private and shared spaces.

3) For ARM cores, there is the added benefit of IO/DMA coherence when using DDR3A.

4) The non-core masters on the device can be configured to access upto 2GB in any part of the 8GB DDR3A space, as opposed to a fixed 512MB on DDR3B.

From a superset platform perspective, DDR3B exists for two reasons:

1) Provide support for wireless co-processors that use small and random accesses that are naturally less efficient for DDR3 EMIFs. This inefficient bandwidth use can be offloaded from DDR3A when using DDR3B.

2) The data being stored there was going to be used by other co-processors instead of the cores which are further away from DDR3B and closer to DDR3A.

2. Are cache coherent maintained by hardware across the A15 and C66x cores?

  • A15 is always coherent with A15 regardless destination memory DDR3A or DDR3B
  • C66x is never coherent with any other master (exception of L1 coherent with L2 when L2 used as SRAM)
  • A15 is coherent with IO such as EDMA when destination memory is MSMC SRAM or DDR3A
  • MSMC supports hardware cache coherence between the ARM CorePac L1/L2 caches and EDMA/IO peripherals for shared SRAM and DDR spaces. This feature allows the sharing of MSMC SRAM and DDR data spaces by these masters on the chip, without having to use explicit software cache maintenance techniques.

MSMC does not support memory coherence for these spaces:

  • EMIF Configuration Space
  • MSMC Configuration Space
  • System Master Port Peripherals/Memory
  • Any memory not directly connected to MSMC, such as DDR3B

The DDR3B then has the following coherent masters and support:

  • A15 core and A15 core - Yes
  • A15 core and EDMA - No
  • A15 core and C66x core - No
  • C66x core and C66x core - No
  • C66x core and EDMA - No
  • To address the most common mistakes on AK2H processors.

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