Dear Champs,
On the AM4372, if I wanted to use EMU0/EMU1 (N23/T24) as GPIOs, will the emulation logic drive these pins between reset and when the bootloader gets a chance to configure the PADCONF registers to set them as GPIOs? The datasheet shows them as H (Hi-Z plus weak PU) for both BALL RESET STATE and BALL RESET REL STATE. The BALL RESET REL MODE is 0 which is EMU0 and EMU1 mode.
So this is probably my lack of understanding but once reset is released, don't these balls function as EMU0 and EMU1 until such time software re-configures the pins as GPIOs? If that's the case, will the emulation logic drive these pins during this time? The EMU0/1 pins are both input and output, not sure when they actually get driven. Let's assume TRST is low all this time.
Thank You
