How to use tda4 pcie's vendor specific capability VSEC?

Hi Jian,

I can't see PCIE0_PCIE_DOWNSTREAM_PULSE_0 interrupt. 

1. You wrote "_INTD_ registers are for EP to create interrupt to RC via legacy interrupt scheme." Did you mean that PCIE0_PCIE_DOWNSTREAM_PULSE_0 interrupt is not controlled by _INTD_ registers? if yes, is PCIE_INTD_STATUS_REG_SYS_1 Register Field Descriptions in datasheet is wrong?

2.How to raise PCIE_DOWNSTREAM_PULSE_0 event? I wrote PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG to 0x300 by both ep local write and host cfg write, but there is no PCIE_DOWNSTREAM_PULSE_0 status in PCIE_INTD_STATUS_REG_SYS_1 and no gic 345 vector raised.

Thanks,

Jun

Jun, 

You are right that PCIE_INTD_STATUS_REG_SYS_1 shall reflect PCIE_DOWNSTREAM_PULSE_x status. I mixed up with another device.

Can you try to first enable the interrupt by writing "1" to Bit 24 of the PCIE_INTD_ENABLE_REG_SYS_1 register? 

regards

Jian

Hi Jian,

I have enabled all bits of PCIE_INTD_ENABLE_REG_SYS_0/PCIE_INTD_ENABLE_REG_SYS_1/PCIE_INTD_ENABLE_REG_SYS_2 before my test, there is no any status be set in PCIE_INTD_STATUS_REG_SYS_0/PCIE_INTD_STATUS_REG_SYS_1/PCIE_INTD_STATUS_REG_SYS_2. 

It should set STATUS_SYS_PCIE_LINK_STATE and PCIE_DOWNSTREAM_PULSE_0 because there is link down to link up change after enable INTD, and I have written VSEC to raise PCIE_DOWNSTREAM_PULSE_0.

I tried  to search INTD usage in TISDK, but there is no INTD be used.(linux SDK has PCIe RC/EP driver but they don't use INTD; RTOS SDK has no PCIe driver).

Can you help to confirm:Does tda4 PCIe support INTD? Have TI verified INTD function?

 Thanks,

Jun

Jun, 

Thanks for the update. Do you happen to know which enabled event caused the link reset? It is not related to the VSEC, I am just curious. 

I can't think of any other steps, so will check with the team and report back on ~2 days.

Jian

Jun, 

Out team verified the subsystem on the test bench. He did confirm that  F0_VSEC_INTERRUPT_OUT is mapped to bit 29 of PCIE_INTD_ENABLE_REG_SYS_1, instead of bit 24. 

so can you redo the test, instead of enabling all bits (though they seems to be okay to be enabled), just enable bit 29. Below is the sequence he used:

1. Enable PCIE_DOWNSTREAM_PULSE by writing “1” in register PCIE_INTD_ENABLE_REG_SYS_1 [Bit 29], this will allow CP_INTD to aggregate   F0_VSEC_INTERRUPT_OUT;
2. Write HTI bit of the PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG register, this will cause the VSEC interrupt. Writing can be either from remote RC or via local interface;
3. We expect to see status bit set in PCIE_INTD_STATUS_REG_SYS_1 register, as well as seeing an interrupt coming to GIC. We had following interrupt connection:

             GIC500_SPI_IN_345          PCIE0_PCIE_DOWNSTREAM_PULSE_0

Sorry i don't have a EVM so you have to test it for me. 

Regards

Jian

Hi Jian,

Thanks your update.

When I change to bit29 from bit24, I can get STATUS_SYS_PCIE_DOWNSTREAM_0 by checking PCIE_INTD_STATUS_REG_SYS_1[29].

But I still can't see GIC500_SPI_IN_345. 

I found there is tisci interrupt source includes PCIE in http://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/irq_sources.html

Should I do some tisci operations to configure it? and how?

Thanks.

Jun.

Jun, 

Since we can generate the interrupt from PCIe, yes, we need to use tisci call to enable it to the GIC. Not sure you already tried using:

    http://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html

let me know the status. sorry for the delay.

Jian

Hi Jian,

Thanks for your reply. 

I don't think TISCI_MSG_RM_IRQ_SET can work because it only support set the irqs which are:

1.from NAVSS0_INTR_ROUTER_0 could set to GIC 74~127

2.from GPIOMUX_INTRTR0 could set to GIC 392~447

3.from NAVSS0_INTR_ROUTER_0 could set to GIC 448~511

4.from CMPEVENT_INTRTR0 could set to GIC 544~559

5.from NAVSS0_INTR_ROUTER_0 could set to GIC 672~731

However, PCIE irqs are from none of above, and they have a fixed GIC vector 344~390.

(I tried set it to a NAVSS0_INTR_ROUTER_0 range (74~127) but get a failure tisci return.)

Does TI has plan to support PCIE ep irq in next SDK I can refer to?

Thanks.

Jun, 

I wasn't aware about the sysfw. Let me check. 

jian