TMP112: I2C Acknowledge Bit Setting Time

Zhou Fang67

Part Number: TMP112

Hi Expert,

We have a question related to TMP112 I2C communication for Acknowledge bit.

Please refer to below capture for I2C communication. Our observation shows that TMP112 will drive SDA low for acknowledgement at the falling edge of 8th SCL clock. At the 8th SCL clock, as we have not released SDA from master side, which cause mid-scale voltage.

Is TMP112 designed for give acknowledge at the falling edge of 8th SCL clock?

Thanks

Zhou

over 6 years ago

0 Jose Arteaga4 over 6 years ago

TI__Expert 5695 points

Hi Zhou,
Thanks for sharing your I2C timming waveforms.
Is this a consisting behavior, what type of platform you are using? (e.g. TMP112EVM or your own MCU and I2C library?)

Regards,
Jose

0 Ren Schackmann over 6 years ago

TI__Mastermind 39425 points

Hi Zhou,

Yes, this is normal behavior for an I2C Slave. The slave device must prepare the data line for ACK (9th clock cycle) prior to rising edge of SCL. Since slave doesn't know SCL frequency, it is designed to take control of SDA after some time (HDDAT) following SCL falling edge. It must do this to satisfy setup timing (SUDAT) of next cycle during high speed communication.

Thanks,
Ren

0 Zhou Fang67 over 6 years ago in reply to Jose Arteaga4

TI__Expert 4250 points

Hi Jose,

It is a consisting behavior. The I2C master is a FPGA. The driver is written by customer.

Thanks.
Zhou

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TMP112: I2C Acknowledge Bit Setting Time