Other Parts Discussed in Thread: , AM62D-Q1, , SYSCONFIG
Hi TI Experts,
Can you provide a List of collaterals that can be referred when starting a custom board hardware design.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Board designers,
The below links are a quick reference to the collaterals that can be referred when starting a custom design.
Device Selection and features
Product Pages
https://www.ti.com/product/AM62P
https://www.ti.com/product/AM62P-Q1
Datasheet
AM62Px Sitara Processors datasheet
https://www.ti.com/lit/pdf/sprsp89
Silicon Errata
AM62Px Sitara Processors Silicon Errata, Silicon Revision 1.0, 1.1
https://www.ti.com/lit/pdf/sprz574
Technical Reference Manual
AM62Px Sitara Processors Technical Reference Manual
https://www.ti.com/lit/pdf/spruj83
Custom Board design:
Hardware Design Considerations
Hardware Design Considerations for Custom Board Using AM62P / AM62P-Q1 Family of Processors
https://www.ti.com/lit/pdf/sprada9
Schematic Design and Review Checklist
AM62Px Processor Family specific checklist (Recommended)
AM62P, AM62P-Q1 Processor Family Schematic Design Guidelines and Schematic Review Checklist
https://www.ti.com/lit/pdf/spradn4
AM62X processor families (For references)
AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Families Schematic, Design Guidelines and Review Checklist
https://www.ti.com/lit/pdf/sprad21
Power Consumption
AM62P Power Estimation Tool
https://www.ti.com/lit/pdf/sprujd9
Evaluation - EVM
SK-AM62P-LP Design Package Folder and Files List (Rev. A)
www.ti.com/.../SK-AM62P-LP
www.ti.com/.../sprt780
SK-AM62P-LP Design File Package
https://www.ti.com/lit/zip/sprr487
Schematics (Reference) for RMII interface
Note: We did functionally validate the common clock configuration. No other clocking options were tested.
Ethernet PHY daughter card
https://www.ti.com/tool/DP83867-EVM-AM
https://www.ti.com/tool/DP83826-EVM-AM2
https://www.ti.com/tool/TIDA-00928
There seems to be a muxed GPMC interface implemented.
https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/TMDXICE3359_SCH.pdf
CAD symbols
CAD symbol specific to the selected device can be chosen from the device product page. Refer below example
https://www.ti.com/product/AM62P#cad-cae-symbols
Ordering & quality
https://www.ti.com/product/AM62P#order-quality
https://www.ti.com/product/AM62P-Q1#order-quality
Package pad diameter and substrate pad dimension
AM62P / AM62P-Q1 -> AMH pkg : ball diameter 0.4mm : substrate pad 0.35mm
The recommendation is 1:1 ratio between PCB pad and substrate pad.
DDR Board Design and Layout Guidelines
AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines
https://www.ti.com/lit/pdf/sprad66
Escape Routing for PCB Design
AM62Px Escape Routing for PCB Design
https://www.ti.com/lit/pdf/sprad96
Design Simulation files
https://www.ti.com/product/AM62P#design-tools-simulation
Simulation files provided includes IBIS, IBIS-AMI, BSDL and Thermal model
AM62Px PDN Target impedance Values:
Voltage Rail | Freq Range | Target Impedance (mOhms) |
VDD_CORE (0.75V) | Low (< 1MHz) | 14.25 |
Mid (1 - 20 MHz) | 23.75 | |
High (20 - 50 MHz) | 47.5 | |
VDD_CORE (0.85V) | Low (< 1MHz) | 12.1125 |
Mid (1 - 20 MHz) | 20.1875 | |
High (20 - 50 MHz) | 40.3750 | |
VDD_DDR (1.1V) | Low (< 1MHz) | 9.8 |
Mid (1 - 20 MHz) | 13.0 | |
High (20 - 50 MHz) | 34.0 |
Note:
We do not include Buck output inductance in PDN simulations.
For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to the AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.
Power Distribution Networks: Implementation and Analysis
Sitara Processor Power Distribution Networks: Implementation and Analysis
https://www.ti.com/lit/pdf/sprac76
High Speed Board design and Signal integrity simulation
https://www.ti.com/lit/pdf/spraar7
https://www.ti.com/lit/pdf/spracn9
SYSCONFIG
DDR subsystem register configuration tool
Technical Documents
Collaterals and application notes
https://www.ti.com/product/AM62P#tech-docs
https://www.ti.com/product/AM62P-Q1#tech-docs
Technical Support
AM62P / AM62P-Q1 Custom board design - FAQs
Previous E2E threads - Keywords AM62Px, AM62P, AM62P-Q1
Starting a new thread
Useful links
Sitara family of processors FAQ master list
Other FAQs
Notes
Regards,
Lavanya M R.
Hi Board designers,
Inputs regarding Package shelf life
Please refer below links
https://www.ti.com/support-quality/quality-policies-procedures/product-shelf-life.html
https://www.ti.com/support-quality/faqs/product-shelf-life-faqs.html
https://www.ti.com/support-quality/reliability/reliability-home.html
https://www.ti.com/lit/an/spraby1a/spraby1a.pdf
https://www.ti.com/lit/pdf/snoa550
https://www.ti.com/lit/an/slva840/slva840.pdf
/cfs-file/__key/communityserver-discussions-components-files/791/Baking-Procedure.pdf
Regards,
Sreenivasa