Frequent Questions

  • [FAQ] PRU Read & Write Latencies

    I am writing a PRU application for a PRU-ICSS device (AM261x, AM263Px, AM263x, AM335x, AM437x, AM57x), PRUSS device (AM62x), or a PRU_ICSSG device (AM24x, AM64x, AM65x). I want to calculate how many clock cycles a read or a write will take. How do I do…

  • [FAQ] AM62A7: Early MCU_I2C and MCU_UART response

    Part Number: AM62A7 Other Parts Discussed in Thread: SK-AM62A-LP Can you let me know the steps I can use to reduce the MCU_I2C & MCU_UART response time using MCU+SDK/FreeRTOS SDK and the method to measure this time?

  • [FAQ] AM6442: MPU ARMv7 configurations for Serial OSPI/QSPI Flash

    Part Number: AM6442 The MPU ARMv7 flash region must be configured with appropriate memory attributes and access permissions to enable flash write operations. Incorrect configurations such as read-only permissions, misaligned region boundaries, or improper…

  • [FAQ] F29H850TU: CAN Module Configuration

    Part Number: F29H850TU Other Parts Discussed in Thread: SYSCONFIG Is there any document explaining CAN module configuration parameters and how to configure these parameters in Sysconfig tool?

  • [FAQ] TPS546E25: How to Change TPS546E25 PMB_ADDR (0xD3) on a Secondary Device in a 2-Phase Configuration

    Part Number: TPS546E25 How to Change TPS546E25 PMB_ADDR (0xD3) on a Secondary Device in a 2-Phase Configuration There are multiple devices on the serial bus and need to change the address from the default pin strap address to avoid conflict

  • [FAQ] TPS546E25: When I write to VOUT_SCALE_LOOP (0x29) on TPS546E25 but the device NACKs and does not change value.

    Part Number: TPS546E25 When I write to VOUT_SCALE_LOOP (0x29) on TPS546E25 but the device NACKs and does not change value.

  • [FAQ] How to boot ECDSA key signed Linux SDK on AM6x SoC

    Part Number: AM62P K3 SoC (AM64x, AM62x...) have a set of One-Time Programmable (OTP) efuses which is anchoring Root-of-Trust (RoT) secure boot chain. Linux SDK supports the RSA key signed secure boot [1]. The FAQ discuss how to enable ECDSA key signed…

  • [FAQ] AM62 devices: How to access MAIN domain MCAN from MCU domain core when using MCU+SDK?

    Other Parts Discussed in Thread: AM62P How can I access MAIN domain MCAN instances (MCAN0/MCAN1) from MCU domain cores (MCU R5F or M4F)?

  • [FAQ] AM62L: How to use RTC driver in MCU+SDK in AM62L?

    Part Number: AM62L Other Parts Discussed in Thread: SYSCONFIG What are the steps to add the RTC driver and test the working in AM62L in MCU+SDK?

  • [FAQ] MSPM0G3507: How to put the ISRs into SRAM for MSPM0 deivces

    Part Number: MSPM0G3507 Use function of DL_Interrupt_registerInterrupt to define all the interrupts that used.(This function will copy the vector table into SRAM then modify the interrupt offset address and modify the interrupt ISR entry address as…

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