Hi Board designers,
Refer below inputs regarding SERDES0 use case.
We have a desire to use the SERDES as a raw interface without a protocol on top. The idea would be to just run 8b/10b and limit our packet size to 10 -40 bits. Is this possible or do…
Part Number: AM6441 Tool/software: Posting on behalf of a custome
In eMMC / SD boot source cases, there is a header that in raw mode, allows specifying a fixed pair of offsets for the boot data (it’s shown as 0x0 / 0x40000000 by default)… that’s good…
Part Number: AM6441 Tool/software: Hello Team
I want to use USB in device (slave) mode on AM64x.
If we are going to use AM64x USB in slave mode always, Is it necessary to use Vbus pin on the chip? Should it be connected to VCC coming from USB connector…
Part Number: AM6441 Tool/software: Hello,
I was just wondering, if the eMMC boot works as well as the OSPI boot with an SBL and application image?
Do I need only to set boot mode and the application runs?
Can someone link me to a good, understandable…
Hi Dominic,
I followed the steps below.
Dominic Rath said: power-down everything, power-up EP, load EP app, power-up RC
Starting the example EP application, the UART terminal print the following output:
Dominic Rath said: "PCIe: EP initialized and waiting…
Part Number: AM6441
Tool/software:
Hello Team
In my previous Post I was running a IPC example with shared memory between R5 and M4 core and sharing UART data. This example worked for me. This was NORTOS based example.
Now I want to try this example but…
Hi Board designers,
The Updated schematics along with the list of files listed below have been uploaded on TI.com
https://www.ti.com/tool/SK-AM64B
https://www.ti.com/lit/zip/sprr460
Please provide your feedback for improvement.
List of files for down…
Hello Ryan,
I assume that you have not done the changes below in your test method , and please confirm.
1. After adding a new entry to sciclient_defaultBoardcfg_rm file for routing 16th Router output to GPIO MUX ROUTER,
did you change a new entry size…
Part Number: AM6441 Other Parts Discussed in Thread: SYSCONFIG Hi TI Experts,
Customer is trying to put a small application run by R5f in the 2MB SRAM shown below.
We think the execution speed is the same as the corresponding clock for the SRAM.
Could…