Part Number: BROADCAST_VIDEO_SERDES_IP Tool/software: We need FPD-LINK four Layout design document to guide EDA ,please help us to find the docement,Thanks.
Hi Rakesh,
Understandable. Yes, checking the #lock pin is a good way as well. When the #lock is low, the PLL of the LMH0340 is locked.
Rakesh Reddy Yara said: Is the serializer output compatible with the MACOM reclocker and driver?
The LMH0340 outputs…
Part Number: LMH0340 Hello Everyone,
Our application is a MIPI to SDI bridge. We are trying to leverage a Lattice semiconductor reference design that converts MIPI to OpenLDI LVDS:
https://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty…
Part Number: LMH0341 Hi team,
I cannot download LMH0341 code through http://www.ti.com/tool/broadcast_video_serdes_ip
Below is the error message.
Thanks,
Miranda
Greetings,
LMH0340 by itself does not support SMPTE292/ It needs either Intel/Altera or Xilink FPGAs. There is example FPGA IP to support Xilinx or Intel FPGAs. Please below note a link to these different FPGA IPs and documentations:
http://www.ti.com…
Hi Went,
Normally FPGA or ASIC performs BT.1120 video framing. LMH0030 does 20 parallel bits serialization and reports any error.
For 1080p/60 support, our only option is to use LMH0340. this option uses either Xilinx or Intel FPGA. Please below note…
Hi David,
Given you don't have control over far end receiver, unfortunately i.MX6 processor cannot be used in this application. As you noted, data gets scrambled and you don't have control over the far end monitor. Our only potential solution is to use…
Greetings, TI provides example IP plus documentation. Please below note example FPGA IP links: www.ti.com/.../broadcast_video_serdes_ip Regards,,nasser
Greetings Ehsan,
Perhaps you meant LMH0341 instead of LMH0340? LMH0341 5-LVDS output pairs get normally connected to the FPGA.
Please below note a link to an example FPGA IP plus documentation that converts from 5-LVDS pairs to 10-bits data.
www.ti…
Greetings Farzad,
Normally LMH0340 and LMH0341 are used with either Xilinx, Intel, or other FPGA to do this conversion. Please below note FPGA IP link that does this conversion and more. Please review these documents so you can get a good overview of…
