I quickly looked through the portfolio, but unfortunately I didn't find a device that would meet this requirement. 3.3V input amplitude is the amplitude of a LVCMOS clock. You might consider CDCLVC1112 if you can supply VDD=3.3V. Kind regards, Lane
Hi Meredith,
Unfortunately we do not have a single chip solution that will meet these requirements. The customer may be interested in CDCLVC1310 or CDCLVC1112. We could propose an alternative multichip solution depending on the application requirements…
Hi David,
The output format of CDCLVP1216 is differential. For a distributor with single-ended output format, I would recommend CDCLVC1112, but it only has 12 outputs.
It may be possible to use the differential output as single ended. First you…
Thank you everyone for your valuable input. I'm hoping to follow best possible design practice in HW design, layout to tackle this and later adjust SCLK frequency to establish reliable communication. I'm wondering if a fan-out buffer would help? like…
Connecting 50 devices to a single SPI master will require considerable design. There are multiple issues to overcome. The 3 most significant are delay, reflections on the clock signal and drive strength. All of these must be resolved for each output driver…
Part Number: LMK04832 Other Parts Discussed in Thread: LMK05028 We are designing a jitter sensitive clock distribution circuit and have to generate three clocks:
- CLK100 = LVPECL, 100MHz fixed
- CLK10 = LVCMOS, 10MHz fixed
- SYNC100 = LVPECL, 10ns…
Part Number: CDCLVC1110 Hello support team,
I have a question regarding CDCLVC11xx.
- Can CDCLVC11xx drive a CMOS IC (Vcc = 3.3 V) whose input capacitance is 20 pF with 50 MHz clock signal?
The period of 50 MHz clock signal is 20 ns. So I think…
