Part Number: AM625 Tool/software: Hello,
How are you supposed to generate a device tree configuration for the AM62x based off of the output of the clock tree tool?
I see that the clock tree tool generates a register dump based off of your current…
Part Number: SYSCONFIG Other Parts Discussed in Thread: AM6442 , AM6411 , AM6422 , AM6412 , AM6421 , AM6441 Tool/software: Hi, do you also plan to integrate the AM64xx clock tree tool into sysconfig offline tool?
Regards, Holger
Part Number: TAS3251 Tool/software: I've done a TAS3251 design, and realized that my MCLK is running much too fast for the type of PCB we're using (400+ MHz).. So, I'm looking into using 3-wire I2S as the SCLK should be a much more manageable 6.144MHz…
Part Number: LMK1D1216 Other Parts Discussed in Thread: LMK1D1204 Tool/software: Hello,
I am working on a clock distribution tree for an instrumentation chassis. Let me first describe the main blocks,
1) Precision LVDS clock oscillator with a clean…
Part Number: AM263P4-Q1 Other Parts Discussed in Thread: SYSCONFIG Tool/software: Hey, is there anything like a clock tree view? For example in systemconfig i don't know, what speed has the PWM clock and how to change it. Also iam not able to change the…
Part Number: AFE58JD48EVM Other Parts Discussed in Thread: CDCM1802 , , LMK04826 Tool/software: Hi,
I would like to understand the clock tree of the AFE58JD48EVM : What is the role of the CDCM1802 component?
The JESD interface between the FPGA and…
Part Number: SYSCONFIG Tool/software: Hi, I switch on the MFCLK in the CLOCK VIEWS->Basic but DL_SYSCTL_enableMFCLK(); function was not added in the .c file.
Regards, Holger
Part Number: TMS320F28P650DK Other Parts Discussed in Thread: SYSCONFIG Tool/software: Hi,
in the TRM under the clocking section the CLB clock tree is reported as follows:
In the CLB section is reported like this:
And in sysconfig like this…
Part Number: SYSCONFIG Tool/software: Standalone SysConfig 1.22.0+3893
mspm0_sdk_2_03_00_07
There seems to discontinuity between values displayed in the clock tree and values entered in SYSCTL module.
All clock tree dividers and summary seem to…
