Looks like this was the problem; CLK must go low before /CS goes low (as shown in timing diagram from spec below.
Traces of updated /CS,CLK, and MOSI (MISO matches MOSI now):
Part Number: DAC80504 Hi Team
Hope can get your support for below questions.
Customer found there is no output when they input any data through SPI interface. they don't change any register which all are in default state after power-on, and we checked…
Part Number: DAC80504 Other Parts Discussed in Thread: TLV320AIC34 Dear All,
Can anyone help out how to get (.tsc of DAC80504) with the help of IBIS Model of DAC80504.& one more thing can i get .tsc of another TI ic i.e,TLV320AIC34.
Thanking yo…
Part Number: DAC80504 We are planning to use DAC80504 in our application. we would want to give reference of 5V to REF pin. Our VDD is +5V. Datasheet says Reference input range can be equal to VDD if REFDIV is enabled. If we enable REFDIV(i.e, REFDIV…
Hi Onurcan, Are you investigating our ISO764xFM? Unfortunately this isolator does not support 50MHz SPI speeds due to propagation delay specs, and we do not have digital isolators which meet this requirement at the moment. I hope this is not an unpleasant…
Part Number: DAC80504 Other Parts Discussed in Thread: DAC60508 Hi team,
When I use DAC80504 EVM software to configure DAC80504 EVM board, I use DSO to observe waveform of SPI interface.
I observe there is a clock cycle before actual write cycle and…
Part Number: DAC80504 Hi
OUT0,OUT1,OUT2 channels work normally, OUT3 voltage from 0V instantaneous to 5V,
What's going to interfere with OUT0,OUT1,OUT2?How much interference?
Thanks!
Part Number: DAC80504 The SBAS871C (August 2017) data sheet illustrates the read timing in Figure 63 but fails to illustrate the start of the read data transaction properly with coordination of CS, SCLK, and read Bit 23.. SCLK is not illustrated properly…
Part Number: DAC80504 HI,
I am trying to interface DAC 80504 with TM4C120ENCPDET using SPI. I am trying to write DAC 0 using the following Procedure.
1. CS LOW
2. COnfig Register write
3. CS HIGH
4. CS LOW
5. Gain Register write
6. CS High…
