Part Number: DP83TC814S-Q1 Tool/software: Hello TI team,
Does it have the risk if the power rails are different between power supply and startup configuration pull-up power?
For example, the VDDA_1/2,VDDMAC, VDDIO is supplied from SYS_3.3V; the startup…
Part Number: DP83TC814S-Q1 Tool/software: Hello TI Team,
1.What is the clock frequency of TX when using RGMII, and is there any difference in link up and link down states respectively? 2. I got the following information by reading the registers, bit13…
Part Number: DP83TC814S-Q1 Tool/software: Hi TI team,
From the SNLA389A – TDR Testing, we can't understand the fault:
1) What's the "Half wire open" and "Peak detect"?
2)0x0310 [5:0]=0x3, it means the fault location in…
Part Number: DP83TC814S-Q1 Tool/software: Hello TI Team,
When I test the Transmitter Output Droop of PMA, I find that the waveform has 67MHz-68MHz ringing.
Is it normal?
Another , could you provide the DP83TC814S-Q1's PMA report for us?
Best Regards…
Hi Wang,
Jingkun Wang said: Does it can increase the time of one packet?
The number of bytes per packet can be changed through register 0x61A, which may help with increasing the time. The IPG can also be increased through register 0x61B.
Jingkun Wang said…
Part Number: DP83TC814S-Q1 Tool/software: Hello Melissa,
As we discussed in below link:
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1373625/dp83tc814s-q1-about-led-configuration-question/5305821?tisearch=e2e-sitesearch&keymatch…
Part Number: DP83TC814S-Q1 Tool/software: Hi team,
1. For DP83TC814S-Q1, if the customer is using RMII slave mode, how should the MCU side be connected when they clock the PHY using an external active crystal?
2. May I ask that why is there a 25 Mhz clock…
Part Number: DP83TC814S-Q1 Tool/software: Hello TI Team,
Now , we have an issue that the SQI is still poor, but it links up normally and pings normally.
`Why is SQI poor?
What does cause SQI poor?
Best Regards!
Wang Jingkun
Part Number: DP83TC814S-Q1 Tool/software: Hello TI Team,
If SoC controls the Pin_3 (RESET_N) (Low --> High), do all registers refresh and resample the straps for Autonomous/Managed, Master/Slave, RGMII/SGMII/etc.. modes?
At this hardware configuration…