Part Number: DP83TG720R-Q1 In DP83TG720R-Q1 datasheet, it has defined the below reset Timing:
we have below questions:
a) Does the VDD contain all the power supplies of VDDA VDDIO VDD1P0 in the figure?
b) VDDA VDDIO VDD1P0 power supply which module…
Part Number: DP83TG720R-Q1 We are using DP83TG720R-Q1 transceiver on our board. As per TI Application Document we had selected 9-2304372-9 (2 pin Automotive connector) for the ethernet communication but the Receptacle 9-2302454-9 is not available for purchase…
Part Number: DP83TG720R-Q1 We are interested in enabling higher voltage isolation in front of the TRD pins of the DP83TG720R-Q1.
Higher voltage rated capacitors result in larger packages.
Can you comment on the minimum functional capacitance for DC blocking…
Part Number: DP83TG720R-Q1 Hello,
Please tell me the description of DLL_EN bit in A2D_REG_48 Register. (Address offset=0x430)
8.6.2.33 A2D_REG_48 Register (Offset = 430h) [Reset = 0960h]
Which is delay enable, 0 or 1?
There is no description in datasheet…
Part Number: DP83TG720R-Q1 Hi Expert,
Now I design a new automotive gateway, use DP83TG720R-Q1 as Gigabit PHY and connect to IFX Aurix TC39x MCU via RGMII interface.
Beside the standard RGMII signals, the AURIX TC399 needs a 125MHz reference clock called…
Part Number: DP83TG720R-Q1 hello,
Are there any 720r mdi eye-diagram requirements? We can't find it through open alliance and IEEE standards, only 100Mbps and 10Gps MDI eye-diagram available.
Regards,
Dongbao
Part Number: DP83TG720R-Q1 Dear Expert,
RGMII protocol version2.0 defines the requirement of RXC and TXC clock is +-50ppm as below show, and also I found the requirement of PHY crystal is +-100ppm.
My questions are:
Why the PHY crystal tolerance are…
Part Number: DP83TG720R-Q1 Hello Expert,
I found the RGMII time requirement(input capacitance and output capacitance ) of Tx_D0/ Tx_D1/Rx_D2/Rx_D3 RGMII data line are different with others data line, my question is why differential TI design behavior on…