Part Number: DRA80M I looked into Trace32 peripheral registers and didn’t find the VTM_TMPSENSE0_STAT register that was pointed out in spruid7e.pdf at 5.2.6.1.2 (Screen shot below)
But I could dump the data pointed out at that address 0x4205 0088…
Part Number: DRA80M Team, posting on behalf of a customer using DRA804M:
"I'm looking at some options for DDR on DRA804:
Option 1: DDR4 - x 16 width : MT40A512M16LY-062E AAT. Use 2 of these to get 2GB and have 1 dedicated for ECC.
Option 2: LPDDR4…
Part Number: DRA80M Hello TI Community,
Can the AM65x / DRA80M device meet Air Pressure and Altitude requirements as follows?
For non-operating states (i.e. the TI device is not powered at all)
From 500m [0.3 miles] (108kPa) below sea level
To 15.24km…
Part Number: DRA80M The PINMUX Tool indicates that the ADC can be operated at 3.3V. However, the datasheet gives the ADC supply an absolute maximum rating of 2V. Which is correct?
Part Number: DRA80M
Tool/software: TI C/C++ Compiler
Hi,
We perform our software build in a VM that is created from scratch. Multiple(4 or more) linking commands run in parallel. Each linking step spends a lot of time bulding the rts lib.
How can I do…
Part Number: DRA80M
Per a customer question, could you please let me know the description of the following registers / data regions that are mentioned in the TRM in the memory map.
Apparently, those symbols are not mentioned anywhere further in the document…
Part Number: DRA80M A customer noted the following to me: In 12.3.3.5.1.1 Hyperflash Access Sequence Table 12-6892 of TRM for Maxwell SPRUIE8C it is mentioned (under step 1):
- Issue a few (16 to 20) reads to the HyperFlash CFI region and ensure that the…
Part Number: DRA80M
Hi Processors Team,
My customer is in the process of putting the ADC in continuous mode, but wants to make sure they are correctly running it in continuous mode. The steps they have followed are below:
Steps for configuration: To…
Part Number: DRA80M Per a customer question, could you please provide the list of registers that need to be modified for the configuration of the DDR PLL. (Especially, the decrease of the clock frequency)
According to TRM, DDR system is integrated from…