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  • RE: CCS/DRA829V: Sample application required for MCU_R5FSS0

    Hi Rizwan, The PDK driver examples use the common linker file. You can find the linker file at psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/build/j721e/linker_r5.lds Regards, Karan

  • RE: Compiler/DRA829V: ADC Data Register Address vs ADC Channel

    Hi, we configured as ADC CH5 and CH6 and included in the ADC_APP . Its working fine as expected. Thanks for the response., Thanks, Muthu

  • RE: DRA829V: Interrupt priority Mask Implementation

    Arslan, there should be control register in VIM for this function. you can refer to Section 6.3.3.6 for VIM functional description and Sec 6.3.4.4 for VIM registers. Please reply back if you can not find them. regards Jian

  • DRA829V: JTAG Configuration Guidance

    • Resolved
    Part Number: DRA829V Hi, I have some concerns on the JTAG implementation in my design as the DRA829

  • RE: DRA829V: Connect Linux on A72 (J7 EVM with GESI) to two PCs

    Hi Michael, The four port on EVM common processor board is QSGMII expansion daughter card. QSGMII is not enabled by default. Refer to below thread for enabling QSGMII. https://e2e.ti.com/support/processors/f/791/t/900935 Regards, Vishal

  • DRA829V: SERDES output terminal scheme is LVDS or CML when it used for SGMII?

    • Resolved
    Part Number: DRA829V Dear Expert. We find SGMII SPEC Rev1.8, then it shows SGMII terminal scheme

  • RE: Compiler/DRA829V: How to read Temperature sensor data of j7

    Hi Muthu, Please refer to the FAQ here: https://e2e.ti.com/support/processors/f/791/t/922224 . It has all the details that you asked for. Regards Karthik

  • DRA829V: How to implement XIP with customer application?

    • Resolved
    Part Number: DRA829V Hi, experts, My customers needs to make their own application XIP with Cypress

  • RE: Compiler/DRA829V: SPI Configuration Verification

    Thanks a lot for Sunil for your support

  • RE: CCS/DRA829V: Eth & EthTrcv MCAL Configuration

    Hi, The MCAL Eth driver supports single TX and single RX channels. Could you please describe what usecase you are trying to enable that requires 8 channels? Also note that there is a single MAC port in CPSW_2G, hence only one instance of EthTrcv is...

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