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Showing 170 results View by: Thread Post Sort by
  • Ahsan Hussain
    Ahsan Hussain
    • 1 month ago
    • Processors
    • Processors forum

    DRA829V: J721E: Programming the DPHY_RX_IF MMRs

    Part Number: DRA829V Hello TI team, We have a use case for Jacinto7 whereby we feed two video streams at 800 Mbps (Output clk 400 MHz) and 1500 Mbps (Output clk 89 MHz) to DPHY_RX0 and DPHY_RX1 modules respectively. TRM contains a programming example...
  • Marcus Frech
    Marcus Frech
    • 1 month ago
    • Processors
    • Processors forum

    DRA829V: Power sequencing VDDAR_MCU

    • Resolved
    Part Number: DRA829V Hi, DRA829 power sequencing describes to ramp up VDDAR_MCU at T1 as well as T2
  • Sebastian Hares
    Sebastian Hares
    • 1 month ago
    • Processors
    • Processors forum

    DRA829V: PCIe Independent to each other?

    TI Thinks Resolved
    Part Number: DRA829V Dear TI Team, can i use the 4xPCIe Modules as Root Port (RP) and/or/mixed End of Point (EP) config? Are all 4 Module independent to each other? Is it possible to have 4x PCIe and Ethernet 4x 10/100 + 1x Gig with the SERDES capability...
  • Vineet Roy
    Vineet Roy
    • 1 month ago
    • Processors
    • Processors forum

    RE: DRA829V: Ethernet firmware issue follow ups

    Hi John, Apologize for the delay in attending to this. Regarding your questions: 1) If UART 2 log is not completed how can they be sure that firmware is loaded successfully? Does UART2 log is not generated from Ethernet switch firmware? There...
  • Vineet Roy
    Vineet Roy
    • 1 month ago
    • Processors
    • Processors forum

    RE: DRA829V: Mixing PRG0/1 blocks for RGMII routing

    PRG0 and PRG1 are interfaces for two PRU-ICSSG instances, what is your use-case in routing like this ? For the dual MAC firmware one ICSSG instance can service two ports (both Rx and Tx) Regards Vineet
  • Shrinath Naik
    Shrinath Naik
    • 2 months ago
    • Processors
    • Processors forum

    DRA829V: [EP2000] main domain spi0 device tree changes

    • Resolved
    Part Number: DRA829V Hi , Please share the device tree changes for main domain spi0 for J7 evm
  • Vineet Roy
    Vineet Roy
    • 1 month ago
    • Processors
    • Processors forum

    RE: DRA829V: How to integrate TI Virtual MAC Ethernet driver with AUTOSAR operating system

    Hi Mohamed, Here's the reply from module owner "UDMA is not underneath AUTOSAR modules so no restriction on UDMA APIs. For the OSAL and interrupt requirements, UDMA is integrated in AUTOSAR compliant way. For example UDMA interrupts are...
  • Stanley Liu
    Stanley Liu
    • 1 month ago
    • Processors
    • Processors forum

    RE: Compiler/DRA829V: Atomic and Exclusive Access Instructions Support

    Those instructions are supported. However, it only monitors state in single core, not dual core. Please refer to ARM Cortex R5F TRM at the below link for detail. https://developer.arm.com/documentation/ddi0460/c/Level-One-Memory-System/Internal-exclusive...
  • Vineet Roy
    Vineet Roy
    • 1 month ago
    • Processors
    • Processors forum

    RE: DRA829V: How to integrate TI Ethernet driver with AUTOSAR operating system

    Hi Mounir, Which Operating system dependency are you referring to ? The examples in MCUSW (TI's MCAL software) use TI-RTOS but the API's and libraries are not OS dependent. Refer to this user guide on API's and usage Regards Vinee...
  • Brad Griffis
    Brad Griffis
    • 2 months ago
    • Processors
    • Processors forum

    DRA829V: AVS Configuration

    TI Thinks Resolved
    Part Number: DRA829V According to the data manual Section 5.4 Recommended Operating Conditions, only VDD_CPU supports AVS. Furthermore there appears to be only a single operating point (OPP) supported. The DM mentions to look at the VTM_DEVINFO_VDn registers...
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