Part Number: DS100MB203 Other Parts Discussed in Thread: DS280DF810 , DS250DF230 , DS560DF810 Tool/software: Gooday,
I have a design that uses the DS100MB203 between a FPGA host and 2 10GBASE-T1 PHYs where the SERDES is configured as 10GBASE-R.
/cfs…
Part Number: DS100MB203
Tool/software:
Goodday
I have a design that uses the DS100MB203SQ/NOPB as a DEMUX/MUX for 10GBASE-R traffic.
0714.UMAR-10G02.pdf
In summary (see the schematic page attached) the left side goes the host FPGA (S_IN/Out…
Part Number: DS100MB203
Hi,
In our application we have to split a 10G ethernet connection(we are choosing about 10Gbase-KR or 10Gbase-R) from one port to two clients.
We exploring possibility to use DS100MB203SQ for this purpose. In particular use…
Part Number: DS100MB203 Other Parts Discussed in Thread: DS110DF410 Dear TI Team:
We have DS100MB203 in our design for 10G-KR mux application,
1. Pls review the SCH attached,Thanks
2. In datasheet, There are three functional mode,Pin control mode…
Part Number: DS100MB203 Dear Sirs,
for a very important project of ours, the customer is asking us the Mean Time Between Failure (MTBF) value for the p/n DS100MB203SQ
Could you please provide to us this data? Thanks on advance
Part Number: DS100MB203 Hi, TI Team
I have some questions about DS100MB203 with your help.I design an Ethernet switch production that it supports 10G serdes signal switch via DS100MB203. IF the pin of SEL is seted to low, and the channel fo DS100MB203…
Part Number: DS100MB203 Hi,
According to spec, Transmit Data to Idle , Input to Output latency is 6.2ns --> Why it's so slow ?
Why CML transition is much faster?
Data is also CML so why there is a difference ? .... what do I miss here?
Thanks…
Part Number: DS100MB203 Dear support engoneer.
I'm technical support in SPT.
Customer requesting latch up test result in qualification test.
Colud you please latch up test was performed in qualification test or not?
And tell me the reason of…
Part Number: DS100MB203
Does MUX support the loopback feature and how do I configure it?
What is the insertion loss of MUX？
Can we know how EQ works by *.sh config files? —— is set by an external PIN or an internal register? In our schematic, EQ…
