Part Number: DS110DF111 Hello,
What is the cap DAC range mentioned in register 0x36? What is the effect of changing it? Is this typically something that is manually changed or should it usually be left with the default value?
Thank you!
Best regards…
Hi Zou,
Thank you for answering my questions and checking in with your team.
I found the following host receiver and module receiver eye mask specifications in the SFF-8431 spec. Based on values X1 and Y1, I found that both the host receiver and module…
Hi Sandra,
Thank you for confirming your use case.
I sent you an E2E friend request. Please accept so I can share the IBIS-AMI model via E2E private message.
I cannot review your SFP+ connector network because it is not a TI part. I can review your DS110DF111…
Part Number: DS110DF111
Hello,
I have a custom a PCB design that involves the DS110DF111 to interface between a processor to Cisco optical switch. I'm currently testing with Cisco Compatible Duplex 10GBASE-ZR/ZW Ethernet 10G Ethernet / 8G FC SFP+ transceivers…
Part Number: DS110DF111 Hello,
Can you please provide some details regarding what SBT does?
My customer found that they need to disable SBT in order to achieve a link in a 10GBase-SR application using SFP+ transceivers.
Best Regards, Brian
Part Number: DS110DF111 Hi TI Team,
For retimer DS110DF111, do we need to write the configuration file whenever the system boots up?
Thanks & regards
Sandra
Part Number: DS110DF111 Hello, the DS110DF111 datasheet states that " The DS110DF111 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of register 0x1f inverts the polarity of the output signal for the…
Part Number: DS110DF111 Hello, I am using the DS110DF111 on a custom PCB design to support a 10G Ethernet application between Ethernet controller (Intel XL710) to SFP+. I cannot get the CDR to lock on CH B. For my set-up, I have a 10G SFP+ AOC cable between…