Part Number: DS100DF410 Other Parts Discussed in Thread: DS110DF410 , DS125DF410 , USB2ANY Hi,
Is it possible to create a 4K HDMI- Signal Eye Monitor with DS100DF410 connected via USBANY to SigCon software ?
Best Regards
Martin
Part Number: DS110DF410 At room temperature, after successful chain construction, the signal is cooled down to low temperature. When the signal reaches -25℃, CRC and port down/up will appear on corresponding ports.
Structure: MAC<- >Re-timer<- > Port…
Part Number: DS110DF410 Other Parts Discussed in Thread: DS110RT410 Dear Sir,
I am choosing DS110DF410SQ for our 10G backplane application. it describes the DFE function. may I know the advantage of DFE?
or for cost issue maybe I just use DS110RT410 is…
Part Number: DS125DF410 Other Parts Discussed in Thread: DS100DF410 , DS110DF410 Hello,
Can I drop DS125DF410 in place of DS100DF410 with no software changes required? The datasheet does not specify which data rate the device defaults to if register 0x2F…
Part Number: DS110DF410 Hi Team,
Please advise me on questions bellows.
According to the datasheet, DS110DF410 tries to optimize CTLE boost level scanning 32 of EQ table Estimating FOM of each EQ index.
Q1. Does the device choose EQ level after scanning…
Part Number: DS110DF410 Hi Team,
How much dB would the DS110DF410 EQ gain setting vary from part to part for each setting ?
We are asked from our customer because they are facing error in some system using at fixed CTLE mode.
Best Regards,
Kawai
Part Number: DS110DF410
Hi Team,
We would like to know the detail about th register REG 0x02 [4:2].
I am understanding that when Bit [5:4] = 11'b, we can judge that CDR is locked. To achieve lock, I believe Bit [3] is also required to be "1", which…
Part Number: DS110DF410 Hi Team,
Please allow me to clarify two things about Channel Register, REG 0x01 [0] : SIG_DET_LOSS_INT.
Q1). Is this bit also cleared at READ ?
Q2). Would this bit be always set at the first valid signal input ? Or, Could this…