Other Parts Discussed in Thread: DS50PCI402 Hello,
Our customer use the DS50PCI402, want to know about the auto Rx detection.
The customer's condition is as follows.
x4 lane ENRXDET=0 RXDETA/B=0 connecting:ASIC---DS50PCI402---end point device
…
Other Parts Discussed in Thread: DS50PCI402 Hello,
Our customer use the DS50PCI402.
The customer checked the link-up test.
After the Link-up is OK, the customer change the configuration of the DS50PCI402 to Low Power mode.
Then the Link-up condition…
Other Parts Discussed in Thread: DS50PCI402 Hello,
Our customer have a link-up issue. The customer use the DS50PCI402 at between ASIC and device. The start up sequence as follows.
power on /PRSNT Low to High /PRENT High to Low reset the ASIC and link…
Hi,
All lanes of the DS50PCI402 will start to perform the Rx Detection function at the same time. If some lanes do not detect right away they could finish at different times. I agree, 18ms is an odd difference between the channels.
Regards,
Lee
Other Parts Discussed in Thread: DS50PCI402 Hi,
I am using the DS50PCI402 IC in my design with 5Gbps speed. I need the device IBIS-AMI model for my simulation.
Whether the IBIS-AMI model is available for this device?. If so, Please share the model…
Other Parts Discussed in Thread: DS50PCI402 Hello,
Our customer uses the DS50PCI402 with SMBus Mode, has question.
When the customer write a register, how should he bias for nPRSNT pin?
Is it High or Low or either?
Regards,
Naoki Aoyama
Other Parts Discussed in Thread: DS50PCI402 Hi,
Our customer is finding the IBIS model for DS50PCI402. If this is available, would you please give us the file ?
Best Regards,
Kato
I am planning on using this device for a single lane PCI express repeater, I assume the ref clock signals bypass this device and go directly to my bridge (PEX8311). Is this correct or should my clock be buffered in some way?
Other Parts Discussed in Thread: DS50PCI402 Hi All,
We have a design using DS50PCI402 PCIe equalizer. There are 3 equalizer parts in the design. The PCIe inputs are from an FPGA and the outputs terminate to a connector. There are 3 unused PCIe pairs…