Part Number: DS92LX1622 i2c works fine until I set the BIST_EN bit (in the BIST register, address 0x24). Then i2c transactions fail (meaning, among other things, I can't see the BIST_ERR register).
Is this expected behavior? Or am I doing something…
Part Number: DS92LX1622 Other Parts Discussed in Thread: DS92LX1621 Hi，
One of my clients encountered an I2C communication problem when using DS92LX1621/DS92LX1622.
When writing data to remote 1622 through 1621, the first 6 CLKS are normal, and the start…
Part Number: DS92LX1622 Other Parts Discussed in Thread: DS92LX1621 , , DS92LV2421 , DS92LX2121 , DS92LV2411 , DS92LX2122 , DS92LV2412 , DS92LV2422 Hello,
I've an application currently using the DS92LX1621/22 SER-DES couple to connect a LVCMOS camera to an FPGA…
Part Number: DS92LX1622ds92lx1622/ds92lx1622设置为camera mode， ser mode=0, deser mode=1, ds92lx1622端BISTEN拉高后，也监测到LOCK信号由低变高，但Rin+和Rin-检测不到波形，始终高电平，请问可以从哪些方面检查问题？
Part Number: DS92LX1622 Other Parts Discussed in Thread: DS92LX1621 Hello,
We are using DS92LX1621 / DS92LX1622 on two seperate boards. We face serial data transmissin errors.
By changing BCC register we can increase and decrease the error.
In the datasheet…
Part Number: DS92LX1622 Hello team,
I received a question from the customer.
Is the jitter measurement point the "change point immediately after the trigger" as shown in the following image?
Regards,
Masa
Part Number: DS92LX1622 Hello Support team,
I'd like to know the tRJIT(Receiver Input Jitter Tolerance) of DS92LX1622.
According to Data Sheet, the tRJIT is 0.53UI Typ. Does it mean TOTAL jitter of received serial data must be less than 0.53UI?
Best…
Part Number: DS92LX1622 Other Parts Discussed in Thread: DS92LX1621 Hello Support team,
The differential input range is defined as 180mV@min.
If the differential input range will be 150mVpp at our system, is it possible that Deserializer DS92LX1622 can…
Part Number: DS92LX1622 Hello, We are having problems with i2c pass through mode of DS92LX162x. When want to access something on far end we get NACK back on the near end i2c bus. While we see ACK on far end i2c bus. We have the following setup: For FPGA…
Part Number: DS92LX1622 Hello Support team,
According to Figure 12 in datasheet p14, we can define VTH/VTL as differential voltage range level.
VTH defines as +90mV@max, VTL does as -90mV@min in CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-) in p.8.
I guess…
