Part Number: LMK04228
Hi team,
I DWIN LMK04228 in a wireless station project for JESD204B. To make sure both PLLs are locked, I think I should set Status_LD2 pin to value 0x03 in register? This might be a simple question, but I'm not sure about the…
Part Number: LMK04228 Other Parts Discussed in Thread: LMK04828 ,
Hi there,
I would like to confirm one thing quickly. My customer is using LMK04228 (LMK04828) for a JESD204B use case. The 245.76MHz device clocks are on clockout0 and clockout2…
Other Parts Discussed in Thread: LMK04228 , LMK5C33216 Hello,
I have an application where I use a 10 MHz reference which will lock a 100 MHz VCXO through a digital PLL.
The equipment will work with an external reference and additionally, it has an…
Part Number: TLV3801 Other Parts Discussed in Thread: DS90LV001 , DS38EP100 , DS80EP100 , DS25BR110 , LMK04228 , I have a few LVDS signals coming off-board. Can I use this part to restore the eye diagram and provide very low jitter for the external LVDS…
Part Number: LMK04828 Other Parts Discussed in Thread: , LMK04228 , LMK04821 , LMK04826 Hello,
We are finalizing a design based on the LMK02828 to drive several ADCs clocks. When checking the possible output formats to connect the clocks, I saw a difference…
Part Number: LMK04828 Other Parts Discussed in Thread: LMK04832 , LMK04821 , LMK04826 , LMK04228 According to the TI spec sheet, the LMK04828 uses a 24-bit SPI transaction length. Can I drive the LMK04828 SPI interface with a 32-bit SPI word and shift…
Other Parts Discussed in Thread: LMK04906 , LMK04228 , LMK04828 , LMK04832 I am looking for a recommendation for a chip to clean up jitter on an LVDS serial MCLK signal from an FPGA. The MCLK frequency is typically between 40 and 80 MHz. The output needs…
Part Number: ADC3683 Other Parts Discussed in Thread: LMK04228 Hi,
We would like some expert advice on the following: we are working on a design where we would connect
15 x ADC3693 to an Intel FPGA (Arria 10). At the FPGA-side the LVDS DDR data is…
Typically the clock from the FPGA is not low jitter. The approach is to use a clock generator that can supply the ADC clock and the synchronized clock to the FPGA. The ADS4142 EVM uses the CDCE72010 clock generator device. You can also check out a device…
