Part Number: SN65DSI84 Tool/software: In SN65DSI84 datasheet, there seems to be confusing for VCORE pin.
1. page 5, 1uF capacitor have to be connected to VCORE.
2. but page 45, 1~10uF capacitor was recommended to connect to VCORE.
I would like to…
Hey Michael,
Michael Schweikart said: I have another 21" Display with a resolution of 1920x1080. Also as dual channel configuration. The resolution register is set to 1920. When i activate the color bar. The color bar is displayed. Why is this the case…
Part Number: SN65DSI84 I am working SN65DSI84 with i.MX93.
I could recognized this SN65DSI84 chip.
But there are some error like below.
Could you let me know what I was wrong?
imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops…
Part Number: SN65DSI84-Q1 Hi team,
What are the requirements for the equal length of DSI and LVDS signals on the layout of SN65DSI84-Q1? The customer's application case is as shown below:
Please also clarify the following questions: For the output…
Part Number: SN65DSI84 Hi team, could this device support dynamic frame adjustment? if not, do we have the device support it? Custom need device from MIPI to LVDS and support dynamic frame adjustment.
Part Number: SN65DSI84 Other Parts Discussed in Thread: SN65DSI83 Tool/software: I am struglling to display from mipi-dsi to dual lvds using sn65dsi84.
It's ok to i2cdetect and device's registry value.
However, the drm_bridge_attach function…
Part Number: SN65DSI84-Q1 Other Parts Discussed in Thread: SN65DSI84 Hi,
I will simulate MIPI D-PHY signal quality and timing with SN65DSI84, but find SN65DSI84 datasheet only has voltage parameter(as below figure), no timing requirement, so what’s the timing…
Part Number: SN65DSI84-Q1 Tool/software: Hi,
Since the data sheet says "LVDS CLK A to CLK B skew 10ps," I understand that the equal delay condition for CLK A and CLK B is 10 ps. Also, since it says "Keep lengths to within 5 mils of each other" between…