Part Number: SN65DSI84-Q1 Other Parts Discussed in Thread: SN65DSI84 , TDA4VH-Q1 Hi Sirs,
Sorry to bother.
We have three kind of LVDS panel, please help to double check whether SN65DSI84 can support? Thanks!!
1280 x RGB x 720 @ 60 fps, 24-bit 16…
Part Number: SN65DSI84 Hi
For Monocular: 1080p @ 60 fps; 4-lane, 2.5 Gb/s DPHY Port A, is it possible to convert the MIPI signal into dual 1080p @ 60 fps LVDS outputs (LVDS A and LVDS B) in a side-by-side configuration?
Part Number: SN65DSI84-Q1 Other Parts Discussed in Thread: SN65DSI84 Hi Team,
Please share SN65DSI84 - sample code using I2C.
Does EN- enable pin tied to Vcc will work or need to be GPIO Driven. As initilization Sequence mentions to make EN Low and…
Part Number: SN65DSI84 Hi
we design a custom board transmiting DSI to the SN65DSI84 device.
the transmiter we use is the Lattice Crosslink device.
reading from the SN65DSI84 we get CRC error and sometime also sync error.
checking the MIPI line…
Part Number: SN65DSI84-Q1 Other Parts Discussed in Thread: SN65DSI83-Q1 , Hello,
Regarding my ticket: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1618174/sn65dsi84-q1-tft-lvds-module-1280-w-x-rgb-x-800-h-compatibility
…
Part Number: SN65DSI84 Other Parts Discussed in Thread: DSI-TUNER We are using the SN65DSI840Q1 chip as a bridge from MIPI to LVDS on MTK Genio-510.
However, it's not working properly, so we need some help to check if the device tree is incorrect. …
Part Number: SN65DSI84 Hello Team,
We have completed functional validation of SN65DSI84 chipset for DSI to Dual LVDS conversion, in our developement board based on Qualcomm QCS615 SoC.
The Panel used for validation was 'G133HAN01.1" from Fortec, which…
Part Number: SN65DSI84 Other Parts Discussed in Thread: SN65DSI83 Tool/software: Hi Team,
Please help to provide the setting file of SN65DSI84 for attached panel spec.
If you can provide DSI setting file, it is ok, too.
Thanks.
Panel.pdf
Part Number: SN65DSI84-Q1 Hi expert,
The main problem is that during seq2, the DSI CLK is operated in HS mode.
However, seq 2 to 8 do not mention any switching, and in actual SoC operation, there can be cases where the clock transitions from HS…
