Part Number: SN74LV165A Other Parts Discussed in Thread: TIDA-01509 Dear Sir,
From TI reference design (TIDA-01509, https://www.ti.com/lit/pdf/tidrvh7 ), the U1 QH pin connect to U2 SER pin.
I am wondering to know what the layout length constraint is between…
Part Number: SN74LV165A Other Parts Discussed in Thread: SN74HCS165 Hi Team,
Customer wants to use our SN74HC165D to replace our SN74LV165ADR because of device shortage. I check the D/S, the spec seems okay. Could you pls help us double check that? Thanks…
Part Number: SN74LV165A From TI reference design schematic, the CLK_INH pin connect to GND directly.
Does that CLK_INH always LOW be fine?
What happen if the SH/LD is "LOW"? Does IC will ignore the CLK and stop output serial data?
Part Number: SN74LV165A Other Parts Discussed in Thread: SN74HCS165 The schematic See link https://note.youdao.com/s/abxHhbAr ,VCC is DC5V. the parameter Δt/ΔV,for VCC=4.5V to 5.5V,the max is 20ns/V. Does it mean the max is 70ns from 0V to 3.5V. The …
Part Number: SN74LV165A Application of SN74LV165,The schematic diagram is as follows。there is a capacitance C86,when C86 is 22pF, the signal SOUT may error, the error rate is 10%(have 200 Circuit board,20 have error, the other 180 have no error). when C86…
Part Number: SN74LV165A Team,
my customer has a question regarding the timing requirement with VCC=3.3V.
Can you please give more details regarding:
The minimum CLK INH output delay from SH/LD# rising edge (Tdly_cs2_low)
The minimum desabling delay of…
Part Number: SN74LV165A Hi team,
For SN74LV165A(TSSOT): Is the default condition of pin 7 high impedance when these pins are not connected?
Best regards,
Wendy
Part Number: SN74LV165A Hi team,
My customer is using the device SN74LV165ADR now. (The schematic is below. the 8SWPK-SW3 is NC(empty)When we test the resistance of R843 and R1897,some boards are 1kohm and some boards are 300ohm. So we remove the resistors and…
Part Number: SN74LV165A I'm using the SN74LV165A in one of my prototype designs and cannot get the Q_H or \Q_H output to change states. The Q_H remains LOW while the \Q_H remains HIGH. Two of my parallel inputs are set HIGH with the rest LOW for this…