Hello,
While we may not have exactly what you're looking for we have several things available to help you get going with the device. On the product folder you'll find links to a Linux driver, and the FW example project from a reference design the…
Part Number: MISTR-3P-POM-AM437X
Hi,
Is it possible to ensure the real time capability while PRU-ICSS accesses the resource on L3/L4?
Though TI has provided a reference design about the SPI firmware on PRU ( http://www.ti.com/tool/TIDEP0033 ),
it is an…
Gunter,
Please refer to the TI design - www.ti.com/.../TIDEP0033 , SPI Master with Signal Path Delay Compensation Reference Design.
www.ti.com/.../tidua38a.pdf
Firmware: www.ti.com/.../tidcag3
There is no plan to merge it into PRU-ICSS industrial sw…
Hi,
The PRU cores within each PRU-ICSS have access to all resources on the K2G SoC. If you follow the steps in TRM Table 11-3376. SPI Master and Slave Mode Initialization, which step (register) that you are not able to write/read back from PRU?
We have…
Part Number: AM4376 Other Parts Discussed in Thread: TIDA-01555
Hi team,
Are we able to implement a master 4/8 bit QSPI on the PRU-ICSS? What would be the QSPI clock speed?
I managed to find the following TI Design showing our PRU-ICSS as a SPI master…
Hello Mauro,
Thanks for reaching out to us.
Regarding your questions:
1. Yes, SPI master should be able to operate the ADC. Please consider the guidelines explained in section 5.1.2 in the user guide, most notably you need to drive the data with the rising…
Hi Mike,
For PRU-SPI speed, you may refer to the document, which notes "the PRU-ICSS firmware integrates the support for the SPI communication link between the AM437x and the ADS8688. The PRU-ICSS firmware supports various frequencies from 1 MHz up to…
