Part Number: TLK10022 Hello all,
For a design in which an aggregation is made from 5 to 10Gbps I am using a TLK10022. I will be using channel A input 0 and 1 (INA0P/N INA1P/N) as the inputs and at the output the HSTXAP/N pins (in 2:1 mode) .
I was wondering…
Part Number: TLK10022 Hi team,
The customer finds that there is a path inputting in LS and outputting from LS drawn in green path. So customer wonders to know how to set register to achieve input in LS and output in LS without via HS. …
Please show me your BER testing page.
When I config that you mentioned above, the BER is not NAN ,but it's always ERROR because error counter is growing. Does this mean the function of TLK10022 is wrong? How to get Error Counter 0 or loopback…
Part Number: TLK10022 Other Parts Discussed in Thread: TXB0108 , LSF0204D Hi,
I am going to manage 8 TLK10022 chips over a common 3V3 MDC/MDIO bus.
Could you suggest a voltage translator/ buffer (3V3 to 1V8), with partial power down mode feature, meaning…
Part Number: TLK10022 Hi,
Is it fair to say if we only use the TX side of the chip (aggregator only) then power consumption will be cut in half, 0.95W instead of 1.9W?
and if we run it at lower speed than 10Gbps would the power be almost cut accordingly…
Part Number: TLK10022 Could you please confirm that INAxN/P and INBxN/P inputs on TLK10022 have built-in 100 OHM termination resistors?
Datasheet is clear about REFCLKxN/P in this regard but nothing mentioning about INAxN/P and INBxN/P.
Part Number: TLK10022 Hello everyone,
Using LNK10022, I want to aggregate bunch of "4 low speed streams each at 1.8Gbps" and make "faster data streams at 7.2Gbps".
Based on below calculation I can use a REF CLK between [150-360] MHz…