Part Number: TLK10022 Hello everyone,
Using LNK10022, I want to aggregate bunch of "4 low speed streams each at 1.8Gbps" and make "faster data streams at 7.2Gbps".
Based on below calculation I can use a REF CLK between [150-360] MHz…
Part Number: TLK10022 Could you please confirm that INAxN/P and INBxN/P inputs on TLK10022 have built-in 100 OHM termination resistors?
Datasheet is clear about REFCLKxN/P in this regard but nothing mentioning about INAxN/P and INBxN/P.
Part Number: TLK10022 I need to aggregate 4 low speed streams each at 1.8Gbps and make a fast stream at 7.2Gbps.
Based on calculator I can use a REF CLK between [150-360] MHz. According to the datasheet the highest is the best to use but I have a hard…
Part Number: TLK10022
Hello,
I have a couple of 7.2Gbps aggregated data streams sent out at TLK10022 HSTX_A/B_P/N outputs and received by Xilinx FPGA at MGTHRXP/N inputs.
Regarding the FPGA RXDATA CLK one option is to use the recovered CLK from the RX…
Part Number: TLK10022 Other Parts Discussed in Thread: TLK10081 My customer is handing me Channel Link (4 diff pairs of data and 1 diff pair of clock at 600Mbps LVDS)... I want to know if I can use the TLK10022 to aggregate them into a single high speed…
Hi Ece,
Thank you for clarifying your proposed system design.
Yes, you can use an external refclk with TLK10022 and TLK10081 instead of a PHY clock output. In the receive direction of the TLK (HS input to LS output), I expect the LS outputs will be in…
Part Number: TLK10002FPGAEVM Hello,
maybe a silly question: The product page of the TLK10002 lists beside the evaluation board a FPGA board, that can be used as source to drive the TLK10002. The evaluation boards of the above mentioned TLK10022, TLK10031…
Part Number: TLK10022 Hi,
we have designed a data aggregator using 5 TLK10022 which we connect to an FPGA (Xilinx Ultrascale). We are having problems reading the information coming from the TLK's (basically we don't get anything). We have checked the…