Part Number: XIO2001 From the datasheet the power down sequence is defined as below. There are no timing elements defined as per the power-up sequence.
Is it necessary that the REFCLK is stopped before the PCIR and Power rails are removed? Is there a…
Part Number: XIO2001 Hi Team,
A Japanese customer request me to post this thread.
the issue as below.
↓
XIO2001 is used on Dell OPtiplex7080,
When I am using PCI bus, the expansion board disappears.
※ PCI to PCI bridge disappeared from the device…
Part Number: XIO2001 Hello Sir:
We have a question about assign I/O address.
Our end customer PCI card needs more I/O resource.
May I assign below address range for PCI card using?
1. 0x2C00~0x2CFF
2. 0x3C00~0x3CFF
3. 0x4C00~0x4CFF
4. 0x5C00~0x5CFF
If…
Part Number: XIO2001 Hi,
Can TI provide IBIS model of XIO2001 ZWS package? Please support us.
We can not find ZWS package on the TI.COM Web.
Thanks and best regards, M.HATTORI
Part Number: XIO2001 Hi Team,
My customer is using the XIO2001, and wanted to confirm our understanding of the trace length requirements.
Our understanding is that the clock signals need to be longer than bus signal traces, and CLKOUT6 needs to be slightly…
Part Number: XIO2001 Hi Nasser,
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1091227/xio2001-pci-to-pci-bridge-disappears-from-pc-device-manager
follow up.
The customer also request technical support from DELL.
He has a small…
Part Number: XIO2001 Hello,
I have question for the Electrical Characteristics of h ysteresis buffer.
I can't find the Electrical Characteristics of hysteresis buffer on datasheet.
Q1:Does the hysteresis buffer have an input transition time (t rise …
Part Number: XIO2001 Hello,
I have some questions about the Configuration Register.
1) How do I set the value of the Slot clock configuration of the 12th bit of the data sheet 8.4.55 Link Status Register? Also, is the initial value 0 or 1?
2) Amateur…
Part Number: XIO2001 Hello,
1. Can you please confirm if device is supported in Uboot and Linux.
2. Also the device can be used with PCIe Interface is connected to a RC / Host and the PCI LOcal Bus side connected to FPGA.
Thanks
Part Number: XIO2001
This is a related question to this post: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/727336/xio2001-power-up-sequence-pcir
It looks like following the EVM design will result in PCIR coming down about the…