Hello team,

I have a question about RXCLK.

If the output of the signal generator is input to RXIN0 when it is not settled, does it affect the frequency output from RXCLK?

The details of the question are as follows,

Good condition…

I have taken the FPGA IP for deserializer and found it is 20-bit data interface where data from IC is 10-bit. I'm using it for SMPTE-259M-C, i.e.., SD SDI standard capture. Again is there any way to use it for 10-bit and also how…

In LMH0071 datasheet, it is mentioned that TI will provide FPGA IP.

Does TI provide FPGA IP for LMH0071 deserializer?  If yes, where can I get it?

In the datasheet with reference to TABLE 1 , does the cross mark refer to features available for the particular part number or not.

I've compiled the Altera fpga code ( NSM_SINGLELINK ) but it's made for a CycloneIII and I've got a NAX10 so I don't know if I've mistranslated the PLL or desializer or something…

LMH0071: supported DVB-ASI Packet mode and Burst mode

Hi,

Our customer is considering LMH0071 and they have a question.
Does LMH0071 support both DVB-ASI Packet mode and Burst mode?

Regards,
Nao

Hi,

I would like to know if my undertanding is correct about the RX[4:0] Data Valid after/before clock (tDVBC, tDVAC) of LMH0071 Deserializer. In the datasheet the minimum tDVBC and tDVAC is 650 ps, but LMH0071…

Hi,

Please let me know how the unused differential inputs of LMH0071 must be properly terminated? Is it fine if both the pins of the pair are connected to ground?

Regards,

Prachi

Hi all,

I have a bad experience using LMH0071 chip in receiving DVB-ASI signal in continuous mode, I want you to tell me is there any thing wrong in my work or this is really the device's limitation which is not…